[XS] Change in coreboot[main]: soc/intel/xeon_sp: Handle GPIO SMIs

[Alicja Michalska (Code Review)]

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84301?usp=email )

Change subject: soc/intel/xeon_sp: Handle GPIO SMIs
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soc/intel/xeon_sp: Handle GPIO SMIs

This patch implements GPIO_SMI_STS handler on Lewisburg.

Change-Id: I906978d2bb2c5e055143aab656e40e06c24ace8d
Signed-off-by: Alicja Michalska 
---
M src/soc/intel/xeon_sp/lbg/Makefile.mk
M src/soc/intel/xeon_sp/smihandler.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/84301/1

diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.mk b/src/soc/intel/xeon_sp/lbg/Makefile.mk
index 5dedc83..7a6b1b3 100644
--- a/src/soc/intel/xeon_sp/lbg/Makefile.mk
+++ b/src/soc/intel/xeon_sp/lbg/Makefile.mk
@@ -4,4 +4,6 @@
 romstage-y += soc_pmutil.c soc_gpio.c
 ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c lockdown.c

+smm-y += soc_gpio.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include
diff --git a/src/soc/intel/xeon_sp/smihandler.c b/src/soc/intel/xeon_sp/smihandler.c
index 7c7cee3..a066a2d 100644
--- a/src/soc/intel/xeon_sp/smihandler.c
+++ b/src/soc/intel/xeon_sp/smihandler.c
@@ -89,6 +89,7 @@
 const smi_handler_t southbridge_smi[SMI_STS_BITS] = {
    [APM_STS_BIT] = smihandler_southbridge_apmc,
    [PM1_STS_BIT] = smihandler_southbridge_pm1,
+	[GPIO_STS_BIT] = smihandler_southbridge_gpi,
 #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE)
    [TCO_STS_BIT] = smihandler_southbridge_tco,
 #endif