Attention is currently required from: Damien Zammit, Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49402 )
Change subject: nb/intel/x4x: Update write leveling comment ......................................................................
nb/intel/x4x: Update write leveling comment
Fix a typo and do some style improvements.
Change-Id: Ibc7e1869faa6b9ae12a51b1c3d209bbd8e54b0d2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/x4x/dq_dqs.c 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/49402/1
diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 82dca44..c6171d9 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -746,19 +746,19 @@ * DDR3 uses flyby topology where the clock signal takes a different path * than the data signal, to allow for better signal intergrity. * Therefore the delay on the data signals needs to account for this. - * This is done by by sampleling the the DQS write (tx) signal back over + * This is done by by sampling the the DQS write (tx) signal back over * the DQ signal and looking for delay values where the sample transitions * from high to low. * Here the following is done: - * - enable write levelling on the first populated rank - * - disable output on other populated ranks - * - start from safe DQS (tx) delays (other transitions can be - * found at different starting values but are generally bad) + * - Enable write levelling on the first populated rank. + * - Disable output on other populated ranks. + * - Start from safe DQS (tx) delays. Other transitions can be + * found at different starting values but are generally bad. * - loop0: decrease DQS (tx) delays until low is sampled, * loop1: increase DQS (tx) delays until high is sampled, - * That way we are sure to hit a low-high transition - * - put all ranks in normal mode of operation again - * - note: All ranks need to be leveled together + * This way, we are sure to have hit a low-high transition. + * - Put all ranks in normal mode of operation again. + * Note: All ranks need to be leveled together. */ void search_write_leveling(struct sysinfo *s) {