Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38640 )
Change subject: cpu: Add microcode at pre-defined address ......................................................................
Patch Set 7:
(3 comments)
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@7 PS6, Line 7: c
Coreboot has native assembly code to update microcode by parsing cbfs, removing the need for microco […]
the assembly code around FSP-T invocation actually finds microcode location and size. However, at that time we do not have CAR (because by definition FSP-T is meant to set it up). So we are limited to register memory only. Unfortunately FSP-T TempRamInit call takes 1 parameter (register) that is a address of a structure. Unfortunately it is not really possible to modify that structure unless you somehow get a temporary storage of some sort. So no it is not possible. If FSP-T would take microcode location as a register, that would have totally worked
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@13 PS6, Line 13: : Also, on current version of FSP-T on Xeons microcode is not optional.
This was also observed on some older FSP1.1 versions, possibly for the same reason. https://blog. […]
I think we all agree we need less blobs not more. I think fake microcode for FSP-T is yet another crutch. What we need is to drop FSP-T for good.
Now then, for servers FSP-T is slightly more complicated that what I have seen on atoms. Since multiple cores come out at the same-time, all of them step into FSP-T and some sort of synchronization is performed there. I have tried to implement FSP-T functionality in regular C code in bootblock. However, I got stuck pretty early. I believe the documentation I was given is incomplete. Long story short, we are working with Intel on trying to get rid of FSP-T for xeons but there is no ETA yet.
However at present time this is crutch we have to live with. Once Intel updates the documentation I am pretty confident we can implement FSP-T.
https://review.coreboot.org/c/coreboot/+/38640/6//COMMIT_MSG@20 PS6, Line 20: TP
That's Tioga Pass, right?
yes