Change in coreboot[master]: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59259 )

Change subject: mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
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mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree

With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.

Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/59259/1

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index 39789be..ca90557 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -55,9 +55,9 @@
    register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE"
    register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE"
    register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE"
-	register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE"
    register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE"
-	register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "PCIE_CLK_FREE"

register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
    register "PcieClkSrcClkReq[1]" = "PCIE_CLK_NOTUSED"