Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29023 )
Change subject: riscv: add support smp_pause / smp_resume ......................................................................
Patch Set 7:
(3 comments)
Thanks!
https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h File src/arch/riscv/include/mcall.h:
https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h@72 PS7, Line 72: /* This function is used to operate msip by memory-mapped */ Can you clarify this comment?
https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c File src/arch/riscv/smp.c:
https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@22 PS7, Line 22: void smp_pause(void) Could you add some comments here, especially that this function never returns.
https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24 PS7, Line 24: if (read_csr(mhartid) == 0) Can we move this check outside of this function to make the flow clearer? Also the hart executing coreboot doesn't necessarily have to be 0