HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32497
Change subject: sb/intel/bd82x6x: Use system_reset() ......................................................................
sb/intel/bd82x6x: Use system_reset()
Use already defined system_reset() function.
Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/southbridge/intel/bd82x6x/early_me.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32497/1
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index edb514b..f82ed3e 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -16,6 +16,7 @@
#include <arch/io.h> #include <device/pci_ops.h> +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> #include <device/pci_def.h> @@ -179,8 +180,7 @@ reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32497 )
Change subject: sb/intel/bd82x6x: Use system_reset() ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32497 )
Change subject: sb/intel/bd82x6x: Use system_reset() ......................................................................
Patch Set 1: Code-Review+1
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32497 )
Change subject: sb/intel/bd82x6x: Use system_reset() ......................................................................
sb/intel/bd82x6x: Use system_reset()
Use already defined system_reset() function.
Change-Id: I6e5aff96e06830931acf700593d3e1689857efdc Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32497 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/southbridge/intel/bd82x6x/early_me.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index edb514b..f82ed3e 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -16,6 +16,7 @@
#include <arch/io.h> #include <device/pci_ops.h> +#include <cf9_reset.h> #include <console/console.h> #include <delay.h> #include <device/pci_def.h> @@ -179,8 +180,7 @@ reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); - outb(0x6, 0xcf9); - halt(); + system_reset(); }
if (((me_fws2 & 0x10) == 0x10) && (me_fws2 & 0x80) == 0x00) {
-
HAOUAS Elyes (Code Review) -
Nico Huber (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)