Change in coreboot[master]: [WIP] arch/riscv: Advance the instruction pointer after handling misa...

[Jonathan Neuschäfer (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/28617

to look at the new patch set (#2).

Change subject: [WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store
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[WIP] arch/riscv: Advance the instruction pointer after handling misaligned load/store

TODO: test!
TODO: clean up

Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling")
Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845
Signed-off-by: Jonathan Neuschäfer 
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M src/arch/riscv/misaligned.c
1 file changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/28617/2