Change in coreboot[master]: soc/amd/cezanne: Get I2C controller infomation

[Bao Zheng (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Zheng Bao, Karthik Ramasubramanian, Felix Held.
Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51025 )

Change subject: soc/amd/cezanne: Get I2C controller infomation
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Patch Set 7:

(2 comments)

File src/soc/amd/cezanne/include/soc/i2c.h:

https://review.coreboot.org/c/coreboot/+/51025/comment/d259791e_51d765e6 
PS6, Line 9: #define GPIO_I2C2_SCL		BIT(2)
           : #define GPIO_I2C3_SCL		BIT(3)
> yes, that should be added for i2c0 and i2c1 too, since those are usable from the x86 side on renoir/ […]

Done

File src/soc/amd/cezanne/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/51025/comment/eeea445c_6f4ac55d 
PS6, Line 20: 2
> this should be 0, since i2c0 and i2c1 are usable from the x86 side in cezanne

Done