Change in coreboot[master]: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification opt...

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45723 )

Change subject: soc/intel/{skl,cnl,icl,jsl,elh,tgl}: make XTAL S0ix qualification optional
......................................................................

Patch Set 3:
> Patch Set 3:
>
> I have some news... checking SKL/KBL, CNL/CFL/CML and ICL/TGL FSP again, I realized, they all set bit 22 of CIR31C (0x31C for SKL/KBL, 0x1B1C for the others) *unconditionally*
>
> That means, my patch here must be reversed - unset the bit when XTAL does not need to run. iow. CB:22237 was the right approach already but is missing a devicetree option.
>
> Further, I've been experimenting on CML with that bit. On clevo/l140cu for some still unknown reason, XTAL needs to run in SlpS0#. When setting XTALSDQDIS=1 (= allow XTAL in SlpS0#), SlpS0# gets entered in s2idle. XTALSDQDIS=0 prevents SlpS0#.
>
> However, that still does not solve the mystery around the meaning of that bit - if it does control the condition in PMC checks for XTAL or if it decides that SlpS0# *shall* shut down XTAL.
>
> More info as soon as I found out why XTAL keeps running on clevo/l140cu o.O

Note: CIR31C == XTALSDQDIS