Change in coreboot[master]: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMem...

[Tim Chu (Code Review)]

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error correction type
in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu 
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
index dc870f1..9f37459 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
@@ -143,21 +143,23 @@
   UINT8    reserved2[22];

UINT8    DdrVoltage;
-  UINT8    reserved3[38];
+  UINT8    reserved3[33];
+  UINT8    RasModesEnabled;                       // RAS modes that are enabled
+  UINT8    reserved4[4];
   UINT8    NumChPerMC;
   UINT8    numberEntries;                         // Number of Memory Map Elements
   SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
-  UINT8    reserved4[2213];
+  UINT8    reserved5[2213];
   MEMMAP_SOCKET Socket[MAX_SOCKET];
-  UINT8    reserved5[1603];
+  UINT8    reserved6[1603];

UINT16  BiosFisVersion;                              // Firmware Interface Specification version currently supported by BIOS

-  UINT8    reserved6[24];
+  UINT8    reserved7[24];

UINT32   MmiohBase;                                   // MMIOH base in 64MB granularity

-  UINT8    reserved7[5];
+  UINT8    reserved8[5];

} SYSTEM_MEMORY_MAP_HOB;

[Tim Chu (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47505

to look at the new patch set (#2).

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu 
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 7 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/2

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 2: Code-Review+1

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 2:

Tim, in the commit message, please also add that MEMMAP_SOCKET structure is now exposed.

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 2: Code-Review+2

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 2: Code-Review+1

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 2:
> Patch Set 2:
>
> Tim, in the commit message, please also add that MEMMAP_SOCKET structure is now exposed.

My mistake, please ignore this. It makes sense to add definitions such as PARTIAL_MIRROR_1LM to this file.

[Tim Chu (Code Review)]

Hello Philipp Deppenwiese, build bot (Jenkins), Frans Hendriks, Jonathan Zhang, Ryback Hung, Johnny Lin, Christian Walter, Angel Pons, Bryant Ou, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47505

to look at the new patch set (#3).

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu 
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 17 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/3

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 3: Code-Review+2

This change conflicts with [CB:47494]. After one is merged, the other one needs to be rebased. Sequence does not matter.

[Tim Chu (Code Review)]

Hello Philipp Deppenwiese, build bot (Jenkins), Frans Hendriks, Jonathan Zhang, Ryback Hung, Johnny Lin, Christian Walter, Angel Pons, Bryant Ou, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47505

to look at the new patch set (#4).

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu 
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 17 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47505/4

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 4: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

Patch Set 4: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47505 )

Change subject: vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in SystemMemoryMapHob
......................................................................

vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob

This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.

Tested=On OCP Delta Lake, the value is expected.

Signed-off-by: Tim Chu 
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505
Reviewed-by: Jonathan Zhang 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
1 file changed, 17 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved
  Jonathan Zhang: Looks good to me, approved

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
index 1a4023f..53b7305 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h
@@ -36,6 +36,16 @@
    0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \
    }

+/* Bit definitions for RasModes */
+#define CH_INDEPENDENT		0
+#define FULL_MIRROR_1LM		BIT0
+#define FULL_MIRROR_2LM		BIT1
+#define CH_LOCKSTEP		BIT2
+#define RK_SPARE		BIT3
+#define PARTIAL_MIRROR_1LM	BIT5
+#define PARTIAL_MIRROR_2LM	BIT6
+#define STAT_VIRT_LOCKSTEP	BIT7
+
 #define MEMTYPE_1LM_MASK       (1 << 0)
 #define MEMTYPE_2LM_MASK       (1 << 1)
 #define MEMTYPE_VOLATILE_MASK  (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK)
@@ -143,21 +153,23 @@
   UINT8    reserved2[22];

UINT8    DdrVoltage;
-  UINT8    reserved3[38];
+  UINT8    reserved3[33];
+  UINT8    RasModesEnabled;                       // RAS modes that are enabled
+  UINT8    reserved4[4];
   UINT8    NumChPerMC;
   UINT8    numberEntries;                         // Number of Memory Map Elements
   SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
-  UINT8    reserved4[2216];
+  UINT8    reserved5[2216];
   MEMMAP_SOCKET Socket[MAX_SOCKET];
-  UINT8    reserved5[1603];
+  UINT8    reserved6[1603];

UINT16  BiosFisVersion;                              // Firmware Interface Specification version currently supported by BIOS

-  UINT8    reserved6[24];
+  UINT8    reserved7[24];

UINT32   MmiohBase;                                   // MMIOH base in 64MB granularity

-  UINT8    reserved7[5];
+  UINT8    reserved8[5];

} SYSTEM_MEMORY_MAP_HOB;