Mark Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972 BRANCH=master TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/43669/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a84e73a..71c5266 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -382,6 +382,10 @@ device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... PS1, Line 385: chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end Please fix indentation.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Mathew King, Duncan Laurie,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43669
to look at the new patch set (#2).
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972 BRANCH=master TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/43669/2
Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... PS1, Line 385: chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end
Please fix indentation.
Updated
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... PS2, Line 386: register "power_saving" = "1" : device pci 00.0 on end Nit: these two lines should be indented one more level
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Mathew King, Duncan Laurie,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43669
to look at the new patch set (#3).
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972 BRANCH=master TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/43669/3
Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... PS2, Line 386: register "power_saving" = "1" : device pci 00.0 on end
Nit: these two lines should be indented one more level
Updated.
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 3: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/1/src/mainboard/google/sarien... PS1, Line 385: chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end
Updated
Done
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/arcada/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43669/2/src/mainboard/google/sarien... PS2, Line 386: register "power_saving" = "1" : device pci 00.0 on end
Updated.
Done
Mathew King has uploaded a new patch set (#4) to the change originally created by Mark Hsieh. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/43669/4
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
Patch Set 4: Code-Review+2
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43669 )
Change subject: mb/google/arcada: Enable bayhub 720 on Arcada ......................................................................
mb/google/arcada: Enable bayhub 720 on Arcada
Add PCIe-eMMC bridge bayhub 720 on Arcada to the devicetree.
BUG=b:157971972 BRANCH=sarien TEST=local build and boot from SATA/PCIe-eMMC storage successfully
Signed-off-by: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com Change-Id: I7e925730e57806e7398684dffd0d3bd1f4f9deeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/43669 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Reviewed-by: Mathew King mathewk@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index a84e73a..7e4da3f 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -382,6 +382,10 @@ device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0