[L] Change in coreboot[master]: soc/intel/alderlake: Add support for CSE timestamp data versions
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73712 )
Change subject: soc/intel/alderlake: Add support for CSE timestamp data versions ......................................................................
soc/intel/alderlake: Add support for CSE timestamp data versions
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1.
BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik bora.guvendik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik subratabanik@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kapil Porwal kapilporwal@google.com Reviewed-by: Dinesh Gehlot digehlot@google.com --- M src/mainboard/google/brya/Kconfig M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/cse_telemetry.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/telemetry.c M src/soc/intel/common/block/include/intelblocks/cse.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry.h A src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h 8 files changed, 202 insertions(+), 127 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1534a54..e588524 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -36,6 +36,7 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 if SOC_INTEL_ALDERLAKE_PCH_P
config BOARD_GOOGLE_BASEBOARD_BRYA def_bool n @@ -44,7 +45,6 @@ select HAVE_SLP_S0_GATE select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50
@@ -59,7 +59,6 @@ select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select TPM_GOOGLE_CR50 select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG
@@ -70,7 +69,6 @@ select HAVE_SLP_S0_GATE select MEMORY_SODIMM select SOC_INTEL_ALDERLAKE_PCH_P - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY select SOC_INTEL_RAPTORLAKE select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_CR50 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 9580419..dbee074 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c
+romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c romstage-y += pcie_rp.c diff --git a/src/soc/intel/alderlake/cse_telemetry.c b/src/soc/intel/alderlake/cse_telemetry.c new file mode 100644 index 0000000..8a92a03 --- /dev/null +++ b/src/soc/intel/alderlake/cse_telemetry.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <intelblocks/cse.h> +#include <timestamp.h> + +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) +{ + s64 start_stamp; + + if (!ts) { + printk(BIOS_ERR, "%s: Failed to insert CSME timestamps\n", __func__); + return; + } + + start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; + + timestamp_add(TS_ME_ROM_START, start_stamp); + timestamp_add(TS_ME_BOOT_STALL_END, + start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); + timestamp_add(TS_ME_ICC_CONFIG_START, + start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); + timestamp_add(TS_ME_HOST_BOOT_PREP_END, + start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); + timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, + start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); +} diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55c9e79..33d703f 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -211,6 +211,20 @@ Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data.
+config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 1 of the CSE timestamp + definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). + +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 2 of the CSE timestamp + definitions, it can be used for Meteor Lake M/P. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default y diff --git a/src/soc/intel/common/block/cse/telemetry.c b/src/soc/intel/common/block/cse/telemetry.c index 5f36360..6502be9 100644 --- a/src/soc/intel/common/block/cse/telemetry.c +++ b/src/soc/intel/common/block/cse/telemetry.c @@ -6,11 +6,11 @@
#define MSEC_TO_USEC(x) (x * 1000)
-static void cbmem_inject_telemetry_data(void) +static void process_cse_telemetry_data(void) { struct cse_boot_perf_rsp cse_perf_data; s64 ts[NUM_CSE_BOOT_PERF_DATA] = {0}; - s64 current_time, start_stamp; + s64 current_time; int zero_point_idx = 0;
/* @@ -60,17 +60,7 @@ }
/* Inject CSME timestamps into the coreboot timestamp table */ - start_stamp = current_time - ts[PERF_DATA_CSME_GET_PERF_RESPONSE]; - - timestamp_add(TS_ME_ROM_START, start_stamp); - timestamp_add(TS_ME_BOOT_STALL_END, - start_stamp + ts[PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC]); - timestamp_add(TS_ME_ICC_CONFIG_START, - start_stamp + ts[PERF_DATA_CSME_POLL_FOR_PMC_PPS_START]); - timestamp_add(TS_ME_HOST_BOOT_PREP_END, - start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); - timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, - start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); + soc_cbmem_inject_telemetry_data(ts, current_time); }
void cse_get_telemetry_data(void) @@ -81,5 +71,5 @@ return; }
- cbmem_inject_telemetry_data(); + process_cse_telemetry_data(); } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c87946f..b39ae7f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -3,6 +3,7 @@ #ifndef SOC_INTEL_COMMON_CSE_H #define SOC_INTEL_COMMON_CSE_H
+#include <intelblocks/cse_telemetry.h> #include <types.h> #include <vb2_api.h>
@@ -210,116 +211,6 @@ CSE_LITE_SKU_PART_UPDATE_SUCCESS = 18, };
-/* Boot performance data */ -enum cse_boot_perf_data { - /* CSME ROM start execution */ - PERF_DATA_CSME_ROM_START = 0, - - /* EC Boot Load Done (CSME ROM starts main execution) */ - PERF_DATA_EC_BOOT_LOAD_DONE = 1, - - /* CSME ROM completed execution / CSME RBE started */ - PERF_DATA_CSME_ROM_COMPLETED = 2, - - /* CSME got ESE Init Done indication from ESE */ - PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, - - /* CSME RBE start PMC patch/es loading */ - PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, - - /* CSME RBE completed PMC patch/es loading */ - PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5, - - /* CSME RBE set "Boot Stall Done" indication to PMC */ - PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, - - /* CSME start poll for PMC PPS register */ - PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7, - - /* PMC set PPS */ - PERF_DATA_PMC_SET_PPS = 8, - - /* CSME BUP start running */ - PERF_DATA_CSME_BUP_START = 9, - - /* CSME set "Host Boot Prep Done" indication to PMC */ - PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10, - - /* CSME starts PHYs loading */ - PERF_DATA_CSME_PHY_LOADING_START = 11, - - /* CSME completed PHYs loading */ - PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12, - - /* PMC indicated CSME that xxPWRGOOD was asserted */ - PERF_DATA_PMC_PWRGOOD_ASSERTED = 13, - - /* PMC indicated CSME that SYS_PWROK was asserted */ - PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14, - - /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */ - PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15, - - /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */ - PERF_DATA_CSME_CPU_BOOT_CONFIG_DONW = 16, - - /* PMC indicated CSME that xxPLTRST was de-asserted */ - PERF_DATA_PMC_PLTRST_DEASSERTED = 17, - - /* PMC indicated CSME that TCO_S0 was asserted */ - PERF_DATA_PMC_TC0_S0_ASSERTED = 18, - - /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ - PERF_DATA_PMC_SENT_CRDA = 19, - - /* ACM Active indication - ACM started its execution */ - PERF_DATA_ACM_START = 20, - - /* ACM Done indication - ACM completed execution */ - PERF_DATA_ACM_DONE = 21, - - /* BIOS sent DRAM Init Done message */ - PERF_DATA_BIOS_DRAM_INIT_DONE = 22, - - /* CSME sent DRAM Init Done message back to BIOS */ - PERF_DATA_CSME_DRAM_INIT_DONE = 23, - - /* CSME completed loading TCSS */ - PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24, - - /* CSME started loading ISH Bringup module */ - PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25, - - /* CSME completed loading ISH Bringup module */ - PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26, - - /* CSME started loading ISH Main module */ - PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27, - - /* CSME completed loading Main module */ - PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28, - - /* BIOS sent "End Of Post" message to CSME */ - PERF_DATA_BIOS_END_OF_POST = 29, - - /* CSME sent "End Of Post" ack message back to BIOS */ - PERF_DATA_CSME_END_OF_POST = 30, - - /* BIOS sent "Core BIOS Done" message to CSME */ - PERF_DATA_BIOS_BIOS_CORE_DONE = 31, - - /* CSME sent "Core BIOS Done" ack message back to BIOS */ - PERF_DATA_CSME_BIOS_CORE_DONE = 32, - - /* CSME reached Firmware Init Done */ - PERF_DATA_CSME_GW_INIT_DONE = 33, - - /* 34 - 62 Reserved */ - - /* Timestamp when CSME responded to BupGetBootData message itself */ - PERF_DATA_CSME_GET_PERF_RESPONSE = 63, -}; - /* CSE boot performance data */ struct cse_boot_perf_rsp { struct mkhi_hdr hdr; @@ -585,6 +476,12 @@ void soc_disable_heci1_using_pcr(void);
/* + * Injects CSE timestamps into cbmem timestamp table. SoC code needs to + * implement it since timestamp definitions differ from SoC to SoC. + */ +void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time); + +/* * Get all the timestamps CSE collected using cse_get_boot_performance_data() and * insert them into the CBMEM timestamp table. */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h new file mode 100644 index 0000000..d45b112 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_H + +#if CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1) +#include "cse_telemetry_v1.h" +#endif + +#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h new file mode 100644 index 0000000..d0c8180 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H + +enum cse_boot_perf_data_v1 { + /* CSME ROM start execution */ + PERF_DATA_CSME_ROM_START = 0, + + /* EC Boot Load Done (CSME ROM starts main execution) */ + PERF_DATA_EC_BOOT_LOAD_DONE = 1, + + /* CSME ROM completed execution / CSME RBE started */ + PERF_DATA_CSME_ROM_COMPLETED = 2, + + /* CSME got ESE Init Done indication from ESE */ + PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, + + /* CSME RBE start PMC patch/es loading */ + PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, + + /* CSME RBE completed PMC patch/es loading */ + PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_COMPLETED = 5, + + /* CSME RBE set "Boot Stall Done" indication to PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, + + /* CSME start poll for PMC PPS register */ + PERF_DATA_CSME_POLL_FOR_PMC_PPS_START = 7, + + /* PMC set PPS */ + PERF_DATA_PMC_SET_PPS = 8, + + /* CSME BUP start running */ + PERF_DATA_CSME_BUP_START = 9, + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 10, + + /* CSME starts PHYs loading */ + PERF_DATA_CSME_PHY_LOADING_START = 11, + + /* CSME completed PHYs loading */ + PERF_DATA_CSME_PHY_LOADING_COMPLETED = 12, + + /* PMC indicated CSME that xxPWRGOOD was asserted */ + PERF_DATA_PMC_PWRGOOD_ASSERTED = 13, + + /* PMC indicated CSME that SYS_PWROK was asserted */ + PERF_DATA_PMC_SYS_PWROK_ASSERTED = 14, + + /* PMC sent "CPU_BOOT_CONFIG" start message to CSME */ + PERF_DATA_PMC_CPU_BOOT_CONFIG_START = 15, + + /* CSME sent "CPU_BOOT_CONFIG" done message to PMC */ + PERF_DATA_CSME_CPU_BOOT_CONFIG_DONE = 16, + + /* PMC indicated CSME that xxPLTRST was de-asserted */ + PERF_DATA_PMC_PLTRST_DEASSERTED = 17, + + /* PMC indicated CSME that TCO_S0 was asserted */ + PERF_DATA_PMC_TC0_S0_ASSERTED = 18, + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 19, + + /* ACM Active indication - ACM started its execution */ + PERF_DATA_ACM_START = 20, + + /* ACM Done indication - ACM completed execution */ + PERF_DATA_ACM_DONE = 21, + + /* BIOS sent DRAM Init Done message */ + PERF_DATA_BIOS_DRAM_INIT_DONE = 22, + + /* CSME sent DRAM Init Done message back to BIOS */ + PERF_DATA_CSME_DRAM_INIT_DONE = 23, + + /* CSME completed loading TCSS */ + PERF_DATA_CSME_LOAD_TCSS_COMPLETED = 24, + + /* CSME started loading ISH Bringup module */ + PERF_DATA_PERF_DATA_CSME_LOAD_ISH_BRINGUP_START = 25, + + /* CSME completed loading ISH Bringup module */ + PERF_DATA_CSME_LOAD_ISH_BRINGUP_DONE = 26, + + /* CSME started loading ISH Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_START = 27, + + /* CSME completed loading Main module */ + PERF_DATA_CSME_LOAD_ISH_MAIN_DONE = 28, + + /* BIOS sent "End Of Post" message to CSME */ + PERF_DATA_BIOS_END_OF_POST = 29, + + /* CSME sent "End Of Post" ack message back to BIOS */ + PERF_DATA_CSME_END_OF_POST = 30, + + /* BIOS sent "Core BIOS Done" message to CSME */ + PERF_DATA_BIOS_BIOS_CORE_DONE = 31, + + /* CSME sent "Core BIOS Done" ack message back to BIOS */ + PERF_DATA_CSME_BIOS_CORE_DONE = 32, + + /* CSME reached Firmware Init Done */ + PERF_DATA_CSME_GW_INIT_DONE = 33, + + /* 34 - 62 Reserved */ + + /* Timestamp when CSME responded to BupGetBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 63, +}; + +#endif // SOC_INTEL_COMMON_CSE_TELEMETRY_V1_H
-
Subrata Banik (Code Review)