Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
sb/intel: Factor out early_smbus.c for ICH7 and newer
There's no need to have a copy of the file on each southbridge, since all of them do exactly the same thing. The northbridge code is what uses these functions, so we also need to add this new header to their files.
Change-Id: Id16929cb9c25b8ec3bd067bf7d7605bce1fad2c5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc D src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc R src/southbridge/intel/common/early_smbus.c A src/southbridge/intel/common/early_smbus.h M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/Makefile.inc D src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc D src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc D src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 33 files changed, 58 insertions(+), 274 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/40271/1
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index e6582ad..f41ac5c 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -13,6 +13,7 @@ #include <lib.h> #include <delay.h> #include <timestamp.h> +#include <southbridge/intel/common/early_smbus.h> #include "gm45.h" #include "chip.h"
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index bb00b14..db7482e 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> +#include <southbridge/intel/common/early_smbus.h> #include "i945.h"
void print_pci_devices(void) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index db6e3b8..dea8e42 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -12,6 +12,7 @@ #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> +#include <southbridge/intel/common/early_smbus.h> #include "raminit.h" #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 2f1ce06..1471549 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -35,6 +35,7 @@ #include <cpu/intel/turbo.h> #include <mrc_cache.h> #include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/common/early_smbus.h> #include <southbridge/intel/common/pmbase.h> #include <delay.h> #include <types.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11..b6826e5 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -14,6 +14,7 @@ #include <timestamp.h> #include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> +#include <southbridge/intel/common/early_smbus.h> #include <southbridge/intel/bd82x6x/pch.h> #include <cpu/x86/msr.h> #include <types.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index f1dc881..147d69d 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -20,11 +20,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ -#else -#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ -#endif +#include <southbridge/intel/common/early_smbus.h> #include <spd.h> #include <string.h> #include <device/dram/ddr2.h> diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 534d110..0c02e5a 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -15,6 +15,7 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index ca4ac74..7964319 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -27,7 +27,7 @@
smm-y += smihandler.c me.c me_8.x.c pch.c
-romstage-y += early_smbus.c me_status.c +romstage-y += me_status.c romstage-y += early_rcba.c romstage-y += early_pch.c
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c deleted file mode 100644 index f3151af..0000000 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/smbus_host.h> -#include "pch.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 18383f6..c1d4ede 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -51,10 +51,6 @@
void enable_usb_bar(void);
-#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index d1b6bf6..7e416d4 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -15,6 +15,9 @@ config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n
+config SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_SMBUS def_bool n select HAVE_DEBUG_SMBUS diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index b48cb8a..d3b10aa 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -17,6 +17,8 @@
all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS) += early_smbus.c + romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/common/early_smbus.c similarity index 80% rename from src/southbridge/intel/i82801gx/early_smbus.c rename to src/southbridge/intel/common/early_smbus.c index 3a1369a..2b9fa66 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/common/early_smbus.c @@ -1,10 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* This file is part of the coreboot project. */
-#include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/smbus_host.h> -#include "i82801gx.h" +#include "early_smbus.h"
uintptr_t smbus_base(void) { @@ -14,10 +15,10 @@ int smbus_enable_iobar(uintptr_t base) { /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); + pci_devfn_t dev = PCI_DEV_SMBUS;
/* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != 0x27da) + if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) return -1;
/* Set SMBus I/O base. */ @@ -37,9 +38,9 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); }
-int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +int smbus_write_byte(unsigned int device, unsigned int address, u8 data) { - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); + return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); }
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) @@ -51,3 +52,8 @@ { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } + +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) +{ + return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); +} diff --git a/src/southbridge/intel/common/early_smbus.h b/src/southbridge/intel/common/early_smbus.h new file mode 100644 index 0000000..a1442d1 --- /dev/null +++ b/src/southbridge/intel/common/early_smbus.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H +#define SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H + +#define PCI_DEV_SMBUS PCI_DEV(0x0, 0x1f, 0x3) + +#define SMBUS_IO_BASE 0x0400 + +#define SMB_BASE 0x20 +#define HOSTC 0x40 + +/* HOSTC bits */ +#define I2C_EN (1 << 2) +#define SMB_SMI_EN (1 << 1) +#define HST_EN (1 << 0) + +#if ENV_ROMSTAGE +int smbus_read_byte(unsigned int device, unsigned int address); +int smbus_write_byte(unsigned int device, unsigned int address, u8 data); +int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); +int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf); +#endif + +#endif /* SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS_H */ diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index e57a3ea..3d7a16c 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -21,6 +21,7 @@ select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 if BOOT_DEVICE_SPI_FLASH select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 27e1630..2322160 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -35,7 +35,6 @@ smm-y += smihandler.c
romstage-y += early_init.c -romstage-y += early_smbus.c romstage-y += early_cir.c
endif diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index b42aeb6..437d3af 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -30,12 +30,6 @@ void i82801gx_early_init(void);
#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); void ich7_setup_cir(void); #endif
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 7f69845..55ab58e 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -15,6 +15,7 @@ config SOUTHBRIDGE_INTEL_I82801IX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 if !BOARD_EMULATION_QEMU_X86_Q35 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMBASE diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc index 3c949f6..6ad3141 100644 --- a/src/southbridge/intel/i82801ix/Makefile.inc +++ b/src/southbridge/intel/i82801ix/Makefile.inc @@ -37,7 +37,6 @@ bootblock-y += early_init.c
romstage-y += early_init.c -romstage-y += early_smbus.c romstage-y += dmi_setup.c
endif diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c deleted file mode 100644 index b118e74..0000000 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/smbus_host.h> -#include "i82801ix.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x2) != PCI_DEVICE_ID_INTEL_82801IB_SMB) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 52a5791..38c9aac 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -199,10 +199,6 @@ void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void);
-#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - #endif #endif
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 1d175ab..0832418 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -15,6 +15,7 @@ config SOUTHBRIDGE_INTEL_I82801JX bool select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_PMCLIB diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 49ef51e..b2548fd 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -33,6 +33,5 @@ smm-y += smihandler.c
romstage-y += early_init.c -romstage-y += early_smbus.c
endif diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c deleted file mode 100644 index 37bae66..0000000 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/smbus_host.h> -#include "i82801jx.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2190279..69bbaa7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -211,14 +211,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
-#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); -#endif void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 2b59134..2c1e60c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -28,6 +28,7 @@ select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_PMCLIB diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index 9f724cc..c4f2b5f 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -39,7 +39,6 @@ smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
romstage-y += early_pch.c -romstage-y += early_smbus.c romstage-y +=../bd82x6x/early_me.c romstage-y +=../bd82x6x/me_status.c romstage-y += early_thermal.c diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c deleted file mode 100644 index 0c99a22..0000000 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/smbus_host.h> -#include "pch.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index fc20660..12d24fa 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -41,13 +41,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void);
-#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int smbus_write_byte(unsigned int device, unsigned int address, u8 data); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -#endif - void early_pch_init(void);
void early_thermal_init(void); diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5974a5f..c46c528 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -10,6 +10,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index cd48586..445e496 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -34,7 +34,7 @@ smm-y += pmutil.c usb_ehci.c usb_xhci.c
bootblock-y += early_pch.c -romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c +romstage-y += early_usb.c early_me.c me_status.c early_pch.c romstage-y += rcba.c pmutil.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c deleted file mode 100644 index f3151af..0000000 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* This file is part of the coreboot project. */ - -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <device/smbus_host.h> -#include "pch.h" - -uintptr_t smbus_base(void) -{ - return SMBUS_IO_BASE; -} - -int smbus_enable_iobar(uintptr_t base) -{ - /* Set the SMBus device statically. */ - pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) - return -1; - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - return 0; -} - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index d583992..254e9ff 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -161,11 +161,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
- -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config);
Hello build bot (Jenkins), Damien Zammit, Patrick Georgi, Martin Roth, Arthur Heymans, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40271
to look at the new patch set (#2).
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
sb/intel: Factor out early_smbus.c for ICH7 and newer
There's no need to have a copy of the file on each southbridge, since all of them do exactly the same thing. Northbridges and a mainboard use these functions, so we also need to add this new header to their files.
Change-Id: Id16929cb9c25b8ec3bd067bf7d7605bce1fad2c5 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/lenovo/x201/romstage.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/ironlake/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc D src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc R src/southbridge/intel/common/early_smbus.c A src/southbridge/intel/common/early_smbus.h M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/Makefile.inc D src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc D src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/Makefile.inc D src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 35 files changed, 60 insertions(+), 274 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/40271/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... File src/southbridge/intel/common/early_smbus.c:
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... PS1, Line 20: device it says device here (not vendor)
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... PS1, Line 21: if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL) please do functional changes in advance. the huge patch would ideally be verifiable with BUILD_TIMELESS (or at least result in easy to compare object files)
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
So some devices have access to `smbus_write_byte()` now?
Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40271/2/src/southbridge/intel/commo... File src/southbridge/intel/common/early_smbus.h:
https://review.coreboot.org/c/coreboot/+/40271/2/src/southbridge/intel/commo... PS2, Line 7: #define PCI_DEV_SMBUS PCI_DEV(0x0, 0x1f, 0x3) Use PCH_DEV_SLOT_LPC here?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... File src/southbridge/intel/common/early_smbus.c:
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... PS1, Line 20: device
it says device here (not vendor)
I think this is wrong on other platforms then
https://review.coreboot.org/c/coreboot/+/40271/1/src/southbridge/intel/commo... PS1, Line 21: if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VENDOR_ID_INTEL)
please do functional changes in advance. the huge patch would ideally be […]
Understood
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
Patch Set 2:
So some devices have access to `smbus_write_byte()` now?
Some platforms will have that wrapper, yes. It was possible to write to SMBus before though, by directly using the smbus functions.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
So some devices have access to `smbus_write_byte()` now?
Some platforms will have that wrapper, yes. It was possible to write to SMBus before though, by directly using the smbus functions.
Yeah, I’d just mention it, when people look through the diff (some diffstat is smaller).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2:
Patch Set 2:
So some devices have access to `smbus_write_byte()` now?
Some platforms will have that wrapper, yes. It was possible to write to SMBus before though, by directly using the smbus functions.
Yeah, I’d just mention it, when people look through the diff (some diffstat is smaller).
I plan on splitting this as requested by Nico anyway.
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/40271 )
Change subject: sb/intel: Factor out early_smbus.c for ICH7 and newer ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Christian Walter (Code Review)
-
Nico Huber (Code Review)
-
Paul Menzel (Code Review)