[XS] Change in coreboot[main]: pc80/rtc: Clear CMOS on errors on S3 resume too

[Bill XIE (Code Review)]

Attention is currently required from: Kyösti Mälkki, Nico Huber.

Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78881?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: pc80/rtc: Clear CMOS on errors on S3 resume too
......................................................................

Patch Set 1:

(1 comment)

File src/drivers/pc80/rtc/option.c:

https://review.coreboot.org/c/coreboot/+/78881/comment/1dbce815_43bd4613 :
PS1, Line 204: 		(CONFIG(STATIC_OPTION_TABLE) && !acpi_is_wakeup_s3())
During CB:78288 I Have considered this, and decided to defer CMOS reset on error to the next boot, for CMOS reset during s3 on GM45 platforms will erase their DRAM training data, making s3 resume fail.

Do we really need to reset CMOS on error during s3 resume?

@Jonathon Hall The ultimate solution fur this may be your proposal in the comment of CB:78288 to exclude the range of memory training data from CMOS checksum.