Change in ...coreboot[master]: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30868 )

Change subject: cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's
......................................................................

cpu/intel/smm/gen1: Add pineview to the check for alt SMRR MSR's

Intel pineview has the same alternative SMRR MSR and
IA32_FEATURE_CONTROL enable bit as core2 CPUs so properly check for
that before enabling this feature.

This also exposes a function to fetch whether alternative SMRR MSR's
ought to be used.

Change-Id: Iccaabfa95b8dc4366b8e7e2c2a526081d4af0efa
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/30868
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/cpu/intel/smm/gen1/smi.h
M src/cpu/intel/smm/gen1/smmrelocate.c
2 files changed, 23 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h
index f4cbbc3..cc6811f 100644
--- a/src/cpu/intel/smm/gen1/smi.h
+++ b/src/cpu/intel/smm/gen1/smi.h
@@ -19,3 +19,5 @@
 u32 northbridge_get_tseg_size(void);
 int cpu_get_apic_id_map(int *apic_id_map);
 void northbridge_write_smram(u8 smram);
+
+bool cpu_has_alternative_smrr(void);
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index 5667648..105b9a4 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -56,17 +56,31 @@
 static struct smm_relocation_params smm_reloc_params;
 static void *default_smm_area = NULL;

-static void write_smrr(struct smm_relocation_params *relo_params)
+/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
+   differently. The MSR are at different location from the rest
+   and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
+bool cpu_has_alternative_smrr(void)
 {
    struct cpuinfo_x86 c;
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return false;
+	switch (c.x86_model) {
+	case 0xf:
+	case 0x17: /* core2 */
+	case 0x1c: /* Bonnell */
+		return true;
+	default:
+		return false;
+	}
+}

+static void write_smrr(struct smm_relocation_params *relo_params)
+{
    printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
           relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-	/* Both model_6fx and model_1067x SMRR function slightly differently
-	   from the rest. The MSR are at different location from the rest
-	   and need to be explicitly enabled. */
-	get_fms(&c, cpuid_eax(1));
-	if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
+
+	if (cpu_has_alternative_smrr()) {
    	msr_t msr;
    	msr = rdmsr(IA32_FEATURE_CONTROL);
    	/* SMRR enabled and feature locked */
@@ -171,7 +185,7 @@
    	/* On model_6fx and model_1067x bits [0:11] on smrr_base
    	   are reserved */
    	get_fms(&c, cpuid_eax(1));
-		if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17))
+		if (cpu_has_alternative_smrr())
    		params->smrr_base.lo = (params->smram_base & rmask);
    	else
    		params->smrr_base.lo = (params->smram_base & rmask)