Change in coreboot[master]: soc/intel/denverton_ns: Hook up SMMSTORE

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

soc/intel/denverton_ns: Hook up SMMSTORE

UNTESTED.

Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e
Signed-off-by: Angel Pons 
---
M src/soc/intel/denverton_ns/smihandler.c
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47450/1

diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 5eecba7..cae8b9b 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -10,6 +10,7 @@
 #include <cpu/intel/em64t100_save_state.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
+#include <smmstore.h>
 #include <spi-generic.h>
 #include <soc/iomap.h>
 #include <soc/soc_util.h>
@@ -197,6 +198,26 @@
    	fast_spi_init();
 }

+static void southbridge_smi_store(void)
+{
+	u8 sub_command, ret;
+	em64t100_smm_state_save_area_t *io_smi =
+		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+	uint32_t reg_ebx;
+
+	if (!io_smi)
+		return;
+	/* Command and return value in EAX */
+	sub_command = (io_smi->rax >> 8) & 0xff;
+
+	/* Parameter buffer in EBX */
+	reg_ebx = io_smi->rbx;
+
+	/* drivers/smmstore/smi.c */
+	ret = smmstore_exec(sub_command, (void *)reg_ebx);
+	io_smi->rax = ret;
+}
+
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
@@ -245,6 +266,10 @@
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
+	case APM_CNT_SMMSTORE:
+		if (CONFIG(SMMSTORE))
+			southbridge_smi_store();
+		break;
    }

mainboard_smi_apmc(reg8);

[Angel Pons (Code Review)]

Hello David Guckian, Vanessa Eusebio, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47450

to look at the new patch set (#3).

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

soc/intel/denverton_ns: Hook up SMMSTORE

Tested on Intel Harcuvar CRB, SMMSTORE is now working.

Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e
Signed-off-by: Angel Pons 
---
M src/soc/intel/denverton_ns/smihandler.c
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47450/3

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/47450/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47450/3//COMMIT_MSG@9 
PS3, Line 9: Tested
How? Change an option in TianoCore?

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
File src/soc/intel/denverton_ns/smihandler.c:

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
PS3, Line 201: static void southbridge_smi_store(void)
             : {
             : 	u8 sub_command, ret;
             : 	em64t100_smm_state_save_area_t *io_smi =
             : 		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
             : 	uint32_t reg_ebx;
             : 
             : 	if (!io_smi)
             : 		return;
             : 	/* Command and return value in EAX */
             : 	sub_command = (io_smi->rax >> 8) & 0xff;
             : 
             : 	/* Parameter buffer in EBX */
             : 	reg_ebx = io_smi->rbx;
             : 
             : 	/* drivers/smmstore/smi.c */
             : 	ret = smmstore_exec(sub_command, (void *)reg_ebx);
             : 	io_smi->rax = ret;
             : }
Is this chip specific?

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
File src/soc/intel/denverton_ns/smihandler.c:

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
PS3, Line 201: static void southbridge_smi_store(void)
             : {
             : 	u8 sub_command, ret;
             : 	em64t100_smm_state_save_area_t *io_smi =
             : 		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
             : 	uint32_t reg_ebx;
             : 
             : 	if (!io_smi)
             : 		return;
             : 	/* Command and return value in EAX */
             : 	sub_command = (io_smi->rax >> 8) & 0xff;
             : 
             : 	/* Parameter buffer in EBX */
             : 	reg_ebx = io_smi->rbx;
             : 
             : 	/* drivers/smmstore/smi.c */
             : 	ret = smmstore_exec(sub_command, (void *)reg_ebx);
             : 	io_smi->rax = ret;
             : }
> Is this chip specific?

I don't think so tbh. IIRC dnv_ns isn't using common code, yet, though. Having a (very short) look at soc/intel/common/block/smm/smihandler.c and src/cpu/x86/smm/smihandler.c I guess that can be deduplicated

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3: Code-Review+1

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/47450/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47450/3//COMMIT_MSG@9 
PS3, Line 9: Tested
> How? Change an option in TianoCore?

I didn't test myself, so I'm not 100% sure. I know that the V2 error message about the com buffer not being installed will be gone away, though.

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
File src/soc/intel/denverton_ns/smihandler.c:

https://review.coreboot.org/c/coreboot/+/47450/3/src/soc/intel/denverton_ns/... 
PS3, Line 201: static void southbridge_smi_store(void)
             : {
             : 	u8 sub_command, ret;
             : 	em64t100_smm_state_save_area_t *io_smi =
             : 		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
             : 	uint32_t reg_ebx;
             : 
             : 	if (!io_smi)
             : 		return;
             : 	/* Command and return value in EAX */
             : 	sub_command = (io_smi->rax >> 8) & 0xff;
             : 
             : 	/* Parameter buffer in EBX */
             : 	reg_ebx = io_smi->rbx;
             : 
             : 	/* drivers/smmstore/smi.c */
             : 	ret = smmstore_exec(sub_command, (void *)reg_ebx);
             : 	io_smi->rax = ret;
             : }
> I don't think so tbh. IIRC dnv_ns isn't using common code, yet, though. […]

The SMM save state version is chip-specific. Arthur wants to deduplicate this so this will eventually be deduplicated.

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

Patch Set 3: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47450 )

Change subject: soc/intel/denverton_ns: Hook up SMMSTORE
......................................................................

soc/intel/denverton_ns: Hook up SMMSTORE

Tested on Intel Harcuvar CRB, SMMSTORE is now working.

Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47450
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Nico Huber 
Reviewed-by: Michael Niewöhner 
---
M src/soc/intel/denverton_ns/smihandler.c
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Paul Menzel: Looks good to me, but someone else must approve
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 5eecba7..cae8b9b 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -10,6 +10,7 @@
 #include <cpu/intel/em64t100_save_state.h>
 #include <device/pci_def.h>
 #include <intelblocks/fast_spi.h>
+#include <smmstore.h>
 #include <spi-generic.h>
 #include <soc/iomap.h>
 #include <soc/soc_util.h>
@@ -197,6 +198,26 @@
    	fast_spi_init();
 }

+static void southbridge_smi_store(void)
+{
+	u8 sub_command, ret;
+	em64t100_smm_state_save_area_t *io_smi =
+		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+	uint32_t reg_ebx;
+
+	if (!io_smi)
+		return;
+	/* Command and return value in EAX */
+	sub_command = (io_smi->rax >> 8) & 0xff;
+
+	/* Parameter buffer in EBX */
+	reg_ebx = io_smi->rbx;
+
+	/* drivers/smmstore/smi.c */
+	ret = smmstore_exec(sub_command, (void *)reg_ebx);
+	io_smi->rax = ret;
+}
+
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
@@ -245,6 +266,10 @@
    		printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
    	}
    	break;
+	case APM_CNT_SMMSTORE:
+		if (CONFIG(SMMSTORE))
+			southbridge_smi_store();
+		break;
    }

mainboard_smi_apmc(reg8);