New patch to review for coreboot: 7eedd07 fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macro
Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7632
-gerrit
commit 7eedd07ca9bc4af28bf7c36b07276b6d7efe60f1 Author: Martin Roth martin.roth@se-eng.com Date: Tue Dec 2 10:49:21 2014 -0700
fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macro
- Update chipset_fsp_util.h to add the UPD_MEMDOWN_CHECK pointing into the PcdMemoryParameters structure. This is baytrail FSP specific, so it's put into the chipset code instead of the 'driver' code. Since some of the values need to be decremented and some do not, a second parameter was added to control this. This macro also does not print out the values as they are printed out separately if memory down is enabled. - Update chipset_fsp_util.c to use the UPD_MEMDOWN_CHECK macro. This makes the code more standardized and easier to read.
Change-Id: I233e45db43af4726cab41f4880f1706cf8abb0b7 Signed-off-by: Martin Roth martin.roth@se-eng.com --- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 141 +++++++++------------- src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h | 8 ++ 2 files changed, 65 insertions(+), 84 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c69076c..05284e2 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -307,92 +307,65 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U printk(BIOS_DEBUG, "Xhci:\t\t\t%s\n", UpdData->PcdEnableXhci?"Enabled":"Disabled");
- /* set memory down parameters */ - if (config->EnableMemoryDown != MEMORY_DOWN_DEFAULT) { - UpdData->PcdMemoryParameters.EnableMemoryDown - = config->EnableMemoryDown - MEMORY_DOWN_DISABLE; - - if (config->DRAMSpeed != DRAM_SPEED_DEFAULT) { - UpdData->PcdMemoryParameters.DRAMSpeed - = config->DRAMSpeed - DRAM_SPEED_800MHZ; - } - if (config->DRAMType != DRAM_TYPE_DEFAULT) { - UpdData->PcdMemoryParameters.DRAMType - = config->DRAMType - DRAM_TYPE_DDR3; - } - if (config->DIMM0Enable != DIMM0_ENABLE_DEFAULT) { - UpdData->PcdMemoryParameters.DIMM0Enable - = config->DIMM0Enable - DIMM0_DISABLE; - } - if (config->DIMM1Enable != DIMM1_ENABLE_DEFAULT) { - UpdData->PcdMemoryParameters.DIMM1Enable - = config->DIMM1Enable - DIMM1_DISABLE; - } - if (config->DIMMDWidth != DIMM_DWIDTH_DEFAULT) { - UpdData->PcdMemoryParameters.DIMMDWidth - = config->DIMMDWidth - DIMM_DWIDTH_X8; - } - if (config->DIMMDensity != DIMM_DENSITY_DEFAULT) { - UpdData->PcdMemoryParameters.DIMMDensity - = config->DIMMDensity - DIMM_DENSITY_1G_BIT; - } - if (config->DIMMBusWidth != DIMM_BUS_WIDTH_DEFAULT) { - UpdData->PcdMemoryParameters.DIMMBusWidth - = config->DIMMBusWidth - DIMM_BUS_WIDTH_8BIT; - } - if (config->DIMMSides != DIMM_SIDES_DEFAULT) { - UpdData->PcdMemoryParameters.DIMMSides - = config->DIMMSides - DIMM_SIDES_1RANK; - } - if (config->DIMMtCL != DIMM_TCL_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtCL = config->DIMMtCL; - if (config->DIMMtRPtRCD != DIMM_TRP_TRCD_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtRPtRCD = config->DIMMtRPtRCD; - if (config->DIMMtWR != DIMM_TWR_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtWR = config->DIMMtWR; - if (config->DIMMtWTR != DIMM_TWTR_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtWTR = config->DIMMtWTR; - if (config->DIMMtRRD != DIMM_TRRD_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtRRD = config->DIMMtRRD; - if (config->DIMMtRTP != DIMM_TRTP_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtRTP = config->DIMMtRTP; - if (config->DIMMtFAW != DIMM_TFAW_DEFAULT) - UpdData->PcdMemoryParameters.DIMMtFAW = config->DIMMtFAW; + /* + * set memory down parameters + * Skip setting values if memory down is disabled + * Skip setting values if FSP is earlier than gold 3 + */ + if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) { + UPD_MEMDOWN_CHECK(EnableMemoryDown, DECREMENT_FOR_DEFAULT); + if (UpdData->PcdMemoryParameters.EnableMemoryDown) { + UPD_MEMDOWN_CHECK(DRAMSpeed, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DRAMType, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMM0Enable, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMM1Enable, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMDWidth, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMDensity, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMBusWidth, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMSides, DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtCL, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtRPtRCD, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtWR, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtWTR, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtRRD, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtRTP, NO_DECREMENT_FOR_DEFAULT); + UPD_MEMDOWN_CHECK(DIMMtFAW, NO_DECREMENT_FOR_DEFAULT);
- printk (BIOS_DEBUG, - "Memory Down Data Existed : %s\n"\ - "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ - "- Type (0: DDR3, 1: DDR3L) : %d\n"\ - "- DIMM0 : %s\n"\ - "- DIMM1 : %s\n"\ - "- Width : x%d\n"\ - "- Density : %dGbit\n" - "- BudWidth : %dbit\n"\ - "- Rank # : %d\n"\ - "- tCL : %02X\n"\ - "- tRPtRCD : %02X\n"\ - "- tWR : %02X\n"\ - "- tWTR : %02X\n"\ - "- tRRD : %02X\n"\ - "- tRTP : %02X\n"\ - "- tFAW : %02X\n" - , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" - , UpdData->PcdMemoryParameters.DRAMSpeed - , UpdData->PcdMemoryParameters.DRAMType - , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" - , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" - , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) - , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) - , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) - , (UpdData->PcdMemoryParameters.DIMMSides) + 1 - , UpdData->PcdMemoryParameters.DIMMtCL - , UpdData->PcdMemoryParameters.DIMMtRPtRCD - , UpdData->PcdMemoryParameters.DIMMtWR - , UpdData->PcdMemoryParameters.DIMMtWTR - , UpdData->PcdMemoryParameters.DIMMtRRD - , UpdData->PcdMemoryParameters.DIMMtRTP - , UpdData->PcdMemoryParameters.DIMMtFAW + printk (BIOS_DEBUG, + "Memory Down Data Existed : %s\n"\ + "- Speed (0: 800, 1: 1066, 2: 1333, 3: 1600): %d\n"\ + "- Type (0: DDR3, 1: DDR3L) : %d\n"\ + "- DIMM0 : %s\n"\ + "- DIMM1 : %s\n"\ + "- Width : x%d\n"\ + "- Density : %dGbit\n" + "- BudWidth : %dbit\n"\ + "- Rank # : %d\n"\ + "- tCL : %02X\n"\ + "- tRPtRCD : %02X\n"\ + "- tWR : %02X\n"\ + "- tWTR : %02X\n"\ + "- tRRD : %02X\n"\ + "- tRTP : %02X\n"\ + "- tFAW : %02X\n" + , (UpdData->PcdMemoryParameters.EnableMemoryDown) ? "Enabled" : "Disabled" + , UpdData->PcdMemoryParameters.DRAMSpeed + , UpdData->PcdMemoryParameters.DRAMType + , (UpdData->PcdMemoryParameters.DIMM0Enable) ? "Enabled" : "Disabled" + , (UpdData->PcdMemoryParameters.DIMM1Enable) ? "Enabled" : "Disabled" + , 8 << (UpdData->PcdMemoryParameters.DIMMDWidth) + , 1 << (UpdData->PcdMemoryParameters.DIMMDensity) + , 8 << (UpdData->PcdMemoryParameters.DIMMBusWidth) + , (UpdData->PcdMemoryParameters.DIMMSides) + 1 + , UpdData->PcdMemoryParameters.DIMMtCL + , UpdData->PcdMemoryParameters.DIMMtRPtRCD + , UpdData->PcdMemoryParameters.DIMMtWR + , UpdData->PcdMemoryParameters.DIMMtWTR + , UpdData->PcdMemoryParameters.DIMMtRRD + , UpdData->PcdMemoryParameters.DIMMtRTP + , UpdData->PcdMemoryParameters.DIMMtFAW ); + } } }
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h index 6df1484..1f4fa74 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.h @@ -50,4 +50,12 @@ /* Revision of the FSP binary */ #define FSP_GOLD3_REV_ID 0x00000303
+#define NO_DECREMENT_FOR_DEFAULT 0 +#define DECREMENT_FOR_DEFAULT 1 + +#define UPD_MEMDOWN_CHECK(member, adjust) \ + if (config->member != UPD_DEFAULT) { \ + UpdData->PcdMemoryParameters.member = config->member - adjust; \ + } + #endif /* CHIPSET_FSP_UTIL_H */
-
Martin Roth