Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50193 )
Change subject: sb,soc/intel: Add wake source fields in GNVS ......................................................................
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/include/soc/nvs.h M src/soc/intel/quark/include/soc/nvs.h M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/include/soc/nvs.h M src/southbridge/intel/i82801gx/acpi/globalnvs.asl M src/southbridge/intel/i82801gx/include/soc/nvs.h M src/southbridge/intel/i82801ix/acpi/globalnvs.asl M src/southbridge/intel/i82801ix/include/soc/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/include/soc/nvs.h M src/southbridge/intel/ibexpeak/acpi/globalnvs.asl M src/southbridge/intel/ibexpeak/include/soc/nvs.h M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/include/soc/nvs.h 15 files changed, 48 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index cffb224..c73b7a7 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -25,6 +25,7 @@ TLVL, 8, /* 0x13 - Throttle Level */ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ + GPEI, 32, /* 0x19 - GPE Wake Source */
/* Device Config */ Offset (0x20), diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 9fb0822..a068d1e 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -25,7 +25,8 @@ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ - u8 rsvd1[7]; + u32 gpei; /* 0x19 - GPE Wake Source */ + u8 rsvd1[3];
/* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h index fee0e42..64378cc 100644 --- a/src/soc/intel/quark/include/soc/nvs.h +++ b/src/soc/intel/quark/include/soc/nvs.h @@ -8,6 +8,10 @@ struct __packed global_nvs { uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ + + /* Required for future unified acpi_save_wake_source. */ + uint32_t pm1i; + uint32_t gpei; };
#endif /* SOC_INTEL_QUARK_NVS_H */ diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index e873f55..25dcfe0 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Offset (0xb2), XHCI, 8,
+ PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + Offset (0xf5), TPIQ, 8, // 0xf5 - trackpad IRQ value CBMC, 32, diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h index 969d592..1c33b0c 100644 --- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h +++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h @@ -97,7 +97,11 @@ u8 rsvd11[6]; /* XHCI */ u8 xhci; - u8 rsvd12[65]; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; + u8 rsvd12[57];
u8 tpiq; /* 0xf5 - trackpad IRQ value */ u32 cbmc; diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index 1e3889b..a3b15b6 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -101,4 +101,6 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index b2a6baa..933921c 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -98,6 +98,10 @@ u8 bten;
u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; };
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */ diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index d2af885..f408a8c 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -103,4 +103,7 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + } diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index 2d4980b..3c9aac9 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -98,6 +98,10 @@ u8 bten;
u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; };
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index d2af885..264b52a 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -103,4 +103,6 @@ DOCK, 8, // 0xf0 - Docking Status BTEN, 8, // 0xf1 - Bluetooth Enable CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source } diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 4325a8c..54c4a2c 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -97,6 +97,10 @@ u8 bten;
u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; };
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl index 949da74..46c6f4f 100644 --- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl +++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl @@ -100,6 +100,9 @@ Offset (0xb2), XHCI, 8, CBMC, 32, + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source + }
/* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h index 5ce88a6..03897cd 100644 --- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h +++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h @@ -100,6 +100,10 @@ u8 xhci;
u32 cbmc; + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; };
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */ diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index 979e084..1b06beb 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -93,6 +93,9 @@
Offset (0xa0), CBMC, 32, // 0xa0 - coreboot mem console pointer + + PM1I, 32, // System Wake Source - PM1 Index + GPEI, 32, // GPE Wake Source }
/* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h index 17ded13..7db206e 100644 --- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h +++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h @@ -73,6 +73,10 @@ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */ + + /* Required for future unified acpi_save_wake_source. */ + u32 pm1i; + u32 gpei; };
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */
-
Kyösti Mälkki (Code Review)