Change in coreboot[master]: soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definition

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59628 )

Change subject: soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definition
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soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definition

The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change
the name of the define to FCH_AOAC_REF_CLK_OK_STATE.

Signed-off-by: Felix Held 
Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/aoac/aoac.c
M src/soc/amd/common/block/include/amdblocks/aoac.h
2 files changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/common/block/aoac/aoac.c b/src/soc/amd/common/block/aoac/aoac.c
index c5f161b..0afd2a1 100644
--- a/src/soc/amd/common/block/aoac/aoac.c
+++ b/src/soc/amd/common/block/aoac/aoac.c
@@ -24,8 +24,8 @@
 bool is_aoac_device_enabled(unsigned int dev)
 {
    uint8_t byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
-	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
-	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
+	byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE);
+	if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_REF_CLK_OK_STATE))
    	return true;
    else
    	return false;
diff --git a/src/soc/amd/common/block/include/amdblocks/aoac.h b/src/soc/amd/common/block/include/amdblocks/aoac.h
index ff5d0db..f4a00c7 100644
--- a/src/soc/amd/common/block/include/amdblocks/aoac.h
+++ b/src/soc/amd/common/block/include/amdblocks/aoac.h
@@ -24,7 +24,7 @@

/* Bit definitions for Device D3 State AOACx0000[41...7f; odd byte addresses] */
 #define   FCH_AOAC_PWR_RST_STATE	BIT(0)
-#define   FCH_AOAC_RST_CLK_OK_STATE	BIT(1)
+#define   FCH_AOAC_REF_CLK_OK_STATE	BIT(1)
 #define   FCH_AOAC_RST_B_STATE		BIT(2)
 #define   FCH_AOAC_DEV_OFF_GATING_STATE	BIT(3)
 #define   FCH_AOAC_D3COLD		BIT(4)