Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18457 )
Change subject: soc/intel/common: Add bootblock common stage file ......................................................................
Patch Set 38:
(2 comments)
https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/basec... File src/soc/intel/common/basecode/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/basec... PS37, Line 39: bootblock_soc_early_init(void)
The platform you mention doesn't support this kind of runtime detection. […]
Great, then it should really make use of the build-time approach :)
https://review.coreboot.org/c/coreboot/+/18457/37/src/soc/intel/common/basec... PS37, Line 102: (CONFIG(PAGING_IN_CACHE_AS_RAM))
you consider 3 lines of code as too different?
w.r.t. APL/GLK, I am talking about the hardware.
Intel "true" SoCs consist of a single die, and their internal bus architecture is primarily IOSF. IOSF has existed for about six or seven SoC generations: Lincroft, Cedarview, Bay Trail, Braswell, Quark, Apollo Lake and Gemini Lake. From what I could gather, IOSF is similar to AMBA on ARM-based platforms (hell, even Quark has an IOSF-to-AHB bridge). To initialize the memory, one has to poke the various IOSF units around the SoC. For example, Bay Trail has: D-Unit (DRAM unit), B-Unit (Memory arbiter), R-Unit (REUT unit)...
On the other hand, the big core platforms use a two-die solution, either using two different packages (S and H series) or a single MCM package (U and Y series). Both dies are connected using either DMI or OPI, which is heavily based on PCIe. To initialize the memory, one would usually poke the MCHBAR. Also, DMI needs to be initialized using DMIBAR (processor side) and RCBA (PCH side).
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Angel Pons (Code Review)