Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37403 )
Change subject: {nb,sb,soc}/amd: use AMD common UMA and RAMTOP block ......................................................................
{nb,sb,soc}/amd: use AMD common UMA and RAMTOP block
TEST=boot PC Engines apu1 and apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I7336fcf7e74d54128d2cb93cea94a59846831124 --- M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/pi/Kconfig M src/northbridge/amd/pi/Makefile.inc D src/northbridge/amd/pi/ramtop.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/memmap.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/southbridge.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/amd/agesa/hudson/Makefile.inc D src/southbridge/amd/agesa/hudson/ramtop.c A src/southbridge/amd/agesa/hudson/sleep.c M src/southbridge/amd/cimx/sb800/Makefile.inc R src/southbridge/amd/cimx/sb800/sleep.c 20 files changed, 40 insertions(+), 251 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37403/1
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a..6b81c8e 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -17,6 +17,7 @@ bool default CPU_AMD_AGESA select CBMEM_TOP_BACKUP + select SOC_AMD_COMMON_BLOCK_RAMTOP
if NORTHBRIDGE_AMD_AGESA
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 38ee5b3..ee88b1b 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -18,6 +18,7 @@ default y if CPU_AMD_PI default n select CBMEM_TOP_BACKUP + select SOC_AMD_COMMON_BLOCK_RAMTOP
if NORTHBRIDGE_AMD_PI
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index ffafc60..61917c9 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
-romstage-y += ramtop.c -postcar-y += ramtop.c -ramstage-y += ramtop.c endif diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c deleted file mode 100644 index 823a15c..0000000 --- a/src/northbridge/amd/pi/ramtop.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <cbmem.h> - -#define CBMEM_TOP_SCRATCHPAD 0x78 - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); -} diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index c5464df..f220c34 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -21,6 +21,7 @@ #include <amdblocks/s3_resume.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/BiosCallOuts.h> +#include <amdblocks/uma.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/northbridge.h> diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e192818..0910b01 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_RAMTOP select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 0fb187d..cbf95b9 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -335,38 +335,6 @@ void fch_pre_init(void); void fch_early_init(void); void set_uart_config(int idx); -/** - * @brief Save the UMA bize - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void);
/* Initialize all the i2c buses that are marked with early init. */ void i2c_soc_early_init(void); diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c index 82d6fb6..ae5a331 100644 --- a/src/soc/amd/picasso/memmap.c +++ b/src/soc/amd/picasso/memmap.c @@ -28,16 +28,6 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h>
-void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 08807f3..1f55302 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/uma.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -29,7 +30,6 @@ #include <romstage_handoff.h> #include <soc/cpu.h> #include <soc/northbridge.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index fe801d4..2bf4791 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -501,27 +501,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index bb297a9..62099d7 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -75,6 +75,7 @@ select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_RAMTOP select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index dd514ab..0555afb 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -350,38 +350,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); void bootblock_fch_early_init(void); void bootblock_fch_init(void); -/** - * @brief Save the UMA bize returned by AGESA - * - * @param size = in bytes - * - * @return none - */ -void save_uma_size(uint32_t size); -/** - * @brief Save the UMA base address returned by AGESA - * - * @param base = 64bit base address - * - * @return none - */ -void save_uma_base(uint64_t base); -/** - * @brief Get the saved UMA size - * - * @param none - * - * @return size in bytes - */ -uint32_t get_uma_size(void); -/** - * @brief Get the saved UMA base - * - * @param none - * - * @return 64bit base address - */ -uint64_t get_uma_base(void); + /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 82d6fb6..ae5a331 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -28,16 +28,6 @@ #include <soc/iomap.h> #include <amdblocks/acpimmio.h>
-void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - return biosram_read32(BIOSRAM_CBMEM_TOP); -} - #if CONFIG(ACPI_BERT) #if CONFIG_SMM_TSEG_SIZE == 0x0 #define BERT_REGION_MAX_SIZE 0x100000 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 044a1b0..1efac82 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <amdblocks/uma.h> #include <device/pci_ops.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -32,7 +33,6 @@ #include <agesa_headers.h> #include <soc/cpu.h> #include <soc/northbridge.h> -#include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index d7a09aa..e75df6e 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -648,27 +648,3 @@ * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 5cb3755..6303b3e 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -23,10 +23,10 @@ romstage-y += early_setup.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c ramtop.c +ramstage-y += resume.c sleep.c
-romstage-y += ramtop.c -postcar-y += ramtop.c +romstage-y += sleep.c +postcar-y += sleep.c
romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c deleted file mode 100644 index 22b291d..0000000 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include "hudson.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return xdata; -} diff --git a/src/southbridge/amd/agesa/hudson/sleep.c b/src/southbridge/amd/agesa/hudson/sleep.c new file mode 100644 index 0000000..2af95df --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/sleep.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include "hudson.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 418110b..ab720c8 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -30,9 +30,9 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
-postcar-y += ramtop.c -romstage-y += ramtop.c -ramstage-y += ramtop.c +postcar-y += sleep.c +romstage-y += sleep.c +ramstage-y += sleep.c
bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/sleep.c similarity index 61% rename from src/southbridge/amd/cimx/sb800/ramtop.c rename to src/southbridge/amd/cimx/sb800/sleep.c index b9fc00d..98d12c7 100644 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ b/src/southbridge/amd/cimx/sb800/sleep.c @@ -25,27 +25,3 @@ tmp = ((tmp & (7 << 10)) >> 10); return (int)tmp; } - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - u32 dword = ramtop; - int nvram_pos = 0xf8, i; /* temp */ - for (i = 0; i < 4; i++) { - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA); - nvram_pos++; - } -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi < 4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi * 8); - xnvram_pos++; - } - return xdata; -}
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37403 )
Change subject: {nb,sb,soc}/amd: use AMD common UMA and RAMTOP block ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37403/1/src/southbridge/amd/agesa/h... File src/southbridge/amd/agesa/hudson/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37403/1/src/southbridge/amd/agesa/h... PS1, Line 29: postcar-y += sleep.c Don't rename the file in this commit. The one function is it can also go into common, I believe.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37403 )
Change subject: {nb,sb,soc}/amd: use AMD common UMA and RAMTOP block ......................................................................
Patch Set 1:
Squash stoneyridge/ and picasso/ with the parent commit CB:37402 with necessary Kconfig changes.
IMHO we can put all the BIOSRAM accessors in the same file.
Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37403 )
Change subject: {nb,sb,soc}/amd: use AMD common UMA and RAMTOP block ......................................................................
Abandoned
Squashed with CB:37402
-
Kyösti Mälkki (Code Review) -
Michał Żygowski (Code Review)