[XL] Change in coreboot[main]: soc/mediatek/common/dp: Move common functions to dptx_common.c

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Yidi Lin.

Yu-Ping Wu has posted comments on this change by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/85860?usp=email )

Change subject: soc/mediatek/common/dp: Move common functions to dptx_common.c
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Patch Set 3:

(11 comments)

File src/soc/mediatek/common/dp/dptx.c:

https://review.coreboot.org/c/coreboot/+/85860/comment/ccdd3037_fad7fe74?usp... :
PS3, Line 15: dptx_link_train_clock_recovery_delay
Looks the same as mt8196's `drm_dp_link_train_clock_recovery_delay`, except that in the edge case (`rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14`) the delay is different (1ms vs 100us). We may ask MTK if the delay can be unified.

https://review.coreboot.org/c/coreboot/+/85860/comment/e395533f_b7ed0884?usp... :
PS3, Line 32: dptx_link_train_channel_eq_delay
Same here.

https://review.coreboot.org/c/coreboot/+/85860/comment/ef41d056_107cc72a?usp... :
PS3, Line 49: dptx_channel_eq_ok
Looks the same as mt8196's `drm_dp_channel_eq_ok`.

https://review.coreboot.org/c/coreboot/+/85860/comment/19d98c1b_5b7aa9e1?usp... :
PS3, Line 425: dptx_set_trainingstart
I think it's also possible to share this with mt8196. The differences are:

1. MT8196 has an extra `dptx_hal_setscramble` call
2. MT8196 doesn't have the `DP_LINKRATE_HBR25` case
3. Common code's `dptx_trainingflow` vs MT8196's `mtk_edp_train_setting + mtk_edp_train_cr + mtk_edp_train_eq`

For #3, `dptx_trainingflow` has a while loop containing calls to `dptx_train_tps1` and `dptx_train_tps2_3`, and I think we can split that into two loops, one for `tps1` (equivalent to mt8196's `mtk_edp_train_cr`) and the other for `tps2_3` (equivalent to mt8196's `mtk_edp_train_eq`).

If you think it's too difficult to share this function, I'm fine with the correct approach.

https://review.coreboot.org/c/coreboot/+/85860/comment/d9fbc6a0_ffd8e379?usp... :
PS3, Line 536: static void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable)
Looks the same as mt8196.

https://review.coreboot.org/c/coreboot/+/85860/comment/9a6172c5_a9c47491?usp... :
PS3, Line 559: dptx_video_config
Can this be shared with mt8196?

File src/soc/mediatek/common/dp/include/soc/dptx_common.h:

https://review.coreboot.org/c/coreboot/+/85860/comment/0bc24288_cb931bfb?usp... :
PS3, Line 50: 			  DP_LANE_CHANNEL_EQ_DONE | \
align

https://review.coreboot.org/c/coreboot/+/85860/comment/8366e7c0_f1d4140d?usp... :
PS3, Line 107:                 
tabs

https://review.coreboot.org/c/coreboot/+/85860/comment/f8e18c5e_53ff3b3a?usp... :
PS3, Line 214: dptx_get_lane_status
If `dptx_channel_eq_ok` is shared with mt8196, then this can be static.

https://review.coreboot.org/c/coreboot/+/85860/comment/8a288dc7_a380254c?usp... :
PS3, Line 217: bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
`dptx_auxwrite_bytes` and `dptx_auxread_bytes` can be static functions.

https://review.coreboot.org/c/coreboot/+/85860/comment/59413120_69756504?usp... :
PS3, Line 221: void dptx_videomute(struct mtk_dp *mtk_dp, bool enable);
             : void dptx_set_dptxout(struct mtk_dp *mtk_dp);
These 2 functions can be static if `dptx_video_enable` is shared with mt8196.