Change in coreboot[master]: soc/intel/common: Move L1_substates_control to pcie_rp.h

[Furquan Shaikh (Code Review)]

Attention is currently required from: Subrata Banik, Patrick Rudolph, EricR Lai.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49295 )

Change subject: soc/intel/common: Move L1_substates_control to pcie_rp.h
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Patch Set 4:

(1 comment)

File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:

https://review.coreboot.org/c/coreboot/+/49295/comment/cca4881f_e162fbf2 
PS4, Line 66: L1_SS_FSP_DEFAULT
Not for this patch series - We have used L1_SS_FSP_DEFAULT because we want to handle the case of boards not setting this config and defaulting to the wrong option (default initialized to 0 i.e. L1_SS_DISABLED). Now that we have chipsettree.cb, we can set up the defaults there i.e. by default the chip config for L1 SS control can be set to L1_SS_L1_2 and we don't need to worry about treating 0 in a special way. Anyways, we can do this later on once we are done with the current series.