[S] Change in coreboot[master]: soc/intel/alderlake: Disable Intel TXT

[Subrata Banik (Code Review)]

Attention is currently required from: Tarun Tuli.

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/71575 )

Change subject: soc/intel/alderlake: Disable Intel TXT
......................................................................

soc/intel/alderlake: Disable Intel TXT

This patch makes the call into TXT lib in order to disable the TXT.

TEST=Able to perform disable_txt and unlock memory which helped to
access VGA framebuffer prior calling into FSP-M.

Signed-off-by: Subrata Banik 
Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/romstage.c
2 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/71575/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 9d950a7..a17950a 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -73,6 +73,7 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select INTEL_GMA_OPREGION_2_1
+	select INTEL_TXT_LIB
    select MRC_SETTINGS_PROTECT
    select PARALLEL_MP_AP_WORK
    select PLATFORM_USES_FSP2_2
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 3ee83bd..8a15b5b 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -19,6 +19,7 @@
 #include <cpu/intel/cpu_ids.h>
 #include <timestamp.h>
 #include <string.h>
+#include <security/intel/txt/txt.h>

#define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
@@ -135,6 +136,8 @@
    smbus_common_init();
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);
+	/* Disable Intel TXT is unsupported or SoC haven't selected the config */
+	disable_intel_txt();

if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
    	dbg_feature_cntrl_init();