Change in coreboot[master]: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046
Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex 1 file changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/1
diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex index 40fccaa..dcae73a 100644 --- a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -1,32 +1,32 @@ -23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 1:
(32 comments)
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 1: 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 2: 48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 3: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 6: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 7: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 8: 00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 9: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 11: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
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https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 13: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 14: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 16: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 17: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
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https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 19: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
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https://review.coreboot.org/c/coreboot/+/42524/1/src/mainboard/intel/tglrvp/... PS1, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DOS line endings
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Shreesh Chhabbi has uploaded a new patch set (#2) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved.
Offset Current value Updated value Analysis 1 0x10 0x11 0x11 is correct SPD spec rev 1.1 5 0x19 0x21 0x21 is correct. 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 0xB5 is correct, 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 0xA is correct, 2 ranks per ch, 16 bits device data width 18 0x05 0x04 0x4 is correct for 4267MTs support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 0xE1 is correct for 4267 MTs support
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex 1 file changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/2
Shreesh Chhabbi has uploaded a new patch set (#3) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved.
Offset Current Updated Analysis 1 0x10 0x11 0x11 is correct SPD spec rev 1.1 5 0x19 0x21 0x21 is correct. 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 0xB5 is correct, 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 0xA is correct, 2 ranks per ch, 16 bits device data width 18 0x05 0x04 0x4 is correct for 4267MTs support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 0xE1 is correct for 4267 MTs support
BUG=b:159319534 TEST=Booted on TGL UP3 RVP with ES2 and QS Parts
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex 1 file changed, 32 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/3
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 3: Code-Review+1
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 4:
(32 comments)
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 1: 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 2: 48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 3: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 5: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 6: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 7: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 8: 00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 9: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 11: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 12: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 13: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 14: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 15: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 16: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 17: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 18: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 19: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 22: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 23: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 24: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 25: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 26: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 27: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 28: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 29: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 31: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
https://review.coreboot.org/c/coreboot/+/42524/4/src/mainboard/intel/tglrvp/... PS4, Line 32: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 DOS line endings
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 4: Code-Review+1
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 4: Code-Review+1
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD file for Micron MT53D1G64D8SQ-046 ......................................................................
Patch Set 4: Code-Review+1
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#5).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex A src/mainboard/intel/tglrvp/spd/Samsung-K4U6E3S4AA-MGCL.spd.hex 2 files changed, 40 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/5
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#6).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/6
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#8).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD file, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet. I am yet to update some fields. It is WIP.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/8
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#9).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD files, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet. I am yet to update some fields. It is WIP.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/9
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#10).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD files, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet. I am yet to update some fields to finalize the changes. It is WIP.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/10
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#12).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD files, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/12
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 12:
Can you add BUG and TEST info in commit message?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42524/12//COMMIT_MSG@12 PS12, Line 12: Can you add BUG and TEST info in commit message?
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#13).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD files, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/13
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/12//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42524/12//COMMIT_MSG@12 PS12, Line 12:
Can you add BUG and TEST info in commit message?
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... PS13, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF i'm curious - why 0xff here instead of 0x00?
Hello build bot (Jenkins), Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Srinidhi N Kaushik, Raj Astekar, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/42524
to look at the new patch set (#15).
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
With previous SPD files, found that QS parts had boot issue. By updating few fields in SPD, boot issues are resolved. These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/15
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 15: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... File src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex:
https://review.coreboot.org/c/coreboot/+/42524/13/src/mainboard/intel/tglrvp... PS13, Line 21: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
i'm curious - why 0xff here instead of 0x00?
You are right. Updated them to zeroes.
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/15//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42524/15//COMMIT_MSG@10 PS15, Line 10: few fields can we have details here.
Shreesh Chhabbi has uploaded a new patch set (#16) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support
BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/42524/16
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 16:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42524/15//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/42524/15//COMMIT_MSG@10 PS15, Line 10: few fields
can we have details here.
Done
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 16: Code-Review+2
Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 16: Code-Review+2
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
Patch Set 16:
Can you please help to merge it?
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42524 )
Change subject: mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP ......................................................................
mainboard/intel/tigerlake: Update SPD files for TGL-UP3 RVP
These changes are according to spd_binary_optimization_volteer_v0.4 sheet.
Offset Current value Updated value Analysis 1 0x10 0x11 As per SPD spec rev 1.1 5 0x19 0x21 16 bits for Row addrs, 10 bits for Column addrs 6 0x95 0xB5 4 die, 2 ch per pkg, Byte 16 signal matrix 12 0x02 0x0A 2 ranks per ch, 16 bits device data width 18 0x05 0x04 4267MHz support 29 0x90 0xC0 HW specific 30 0x06 0x68 HW specific 31 0xD0 0x60 HW specific 32 0x02 0x04 HW specific 125 0x00 0xE1 4267MHz support
BUG=b:159319534 TEST=Tested multiple cold boot cycles on TGL-UP3 with QS silicon
Change-Id: Ie506fbfe86a3ffb77763e8d9ef7e8aa69ea44bd3 Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42524 Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Reviewed-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Reviewed-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex M src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex 2 files changed, 10 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Ravishankar Sarawadi: Looks good to me, approved Srinidhi N Kaushik: Looks good to me, approved Shreesh Chhabbi: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex index 40fccaa..946bcc0 100644 --- a/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Micron-MT53D1G64D8SQ-046.spd.hex @@ -1,11 +1,11 @@ -23 10 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 -48 00 05 FF 92 55 00 00 8C 00 90 A8 90 90 06 D0 -02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 55 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex index 945b2e8..946bcc0 100644 --- a/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex +++ b/src/mainboard/intel/tglrvp/spd/Samsung-K4UBE3D4AA-MGCL.spd.hex @@ -1,11 +1,11 @@ 23 11 11 0E 15 21 B5 08 00 40 00 00 0A 21 00 00 -48 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 E0 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -18,8 +18,8 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 -20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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build bot (Jenkins) (Code Review) -
Caveh Jalali (Code Review)
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Patrick Georgi (Code Review)
-
Ravishankar Sarawadi (Code Review)
-
Shreesh Chhabbi (Code Review)
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Srinidhi N Kaushik (Code Review)
-
Wonkyu Kim (Code Review)