Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code

[Aamir Bohra (Code Review)]

Attention is currently required from: V Sowmya, Martin Roth, Sugnan Prabhu S, Tim Wawrzynczak, Subrata Banik, Balaji Manigandan.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 )

Change subject: mb/intel/shadowmountain: Add bootblock and verstage code
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Patch Set 2:

(3 comments)

File src/mainboard/intel/shadowmountain/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/49479/comment/82f7acef_dc31f8ef 
PS2, Line 7: 
           : romstage-$(CONFIG_CHROMEOS) += chromeos.c
           : 
           : ramstage-$(CONFIG_CHROMEOS) += chromeos.c
           : 
later with ramstage/romstage phase?

File src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c:

https://review.coreboot.org/c/coreboot/+/49479/comment/6881bf3d_0c65f22c 
PS2, Line 8: early_gpio_table
Need to add memstrap gpios, TPM Gpios

File src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h:

https://review.coreboot.org/c/coreboot/+/49479/comment/52610ce2_af967cf3 
PS2, Line 13: GPP_B11
chromeos.c marked it as todo?