Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69693 )
Change subject: [TEST] test firmware for crasskneto ......................................................................
[TEST] test firmware for crasskneto
Change-Id: I6b9c90abe562768ea2afff5608a8cfac764569d5 --- M src/mainboard/google/brya/variants/craask/fw_config.c M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 3 files changed, 151 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/69693/1
diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index 5b8f058..8ac399b 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -2,6 +2,7 @@
#include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <console/console.h> #include <fw_config.h>
@@ -51,27 +52,33 @@
void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); - gpio_padbased_override(padbased_table, lte_disable_pads, + + const uint32_t id = board_id(); + + if (id < 0x20) { + + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); - } + }
- if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { - printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); - gpio_padbased_override(padbased_table, wfc_disable_pads, + if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) { + printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n"); + gpio_padbased_override(padbased_table, wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads)); - } + }
- if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { - printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); - gpio_padbased_override(padbased_table, sd_disable_pads, + if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) { + printk(BIOS_INFO, "Disable SD card GPIO pins.\n"); + gpio_padbased_override(padbased_table, sd_disable_pads, ARRAY_SIZE(sd_disable_pads)); - } + }
- if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { - printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); - gpio_padbased_override(padbased_table, stylus_disable_pads, + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { + printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); + gpio_padbased_override(padbased_table, stylus_disable_pads, ARRAY_SIZE(stylus_disable_pads)); + } } } diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index f075ba0..fa0a6ee 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -2,6 +2,7 @@
#include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <boardid.h> #include <commonlib/helpers.h> #include <soc/gpio.h>
@@ -41,6 +42,57 @@ PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), };
+/* Pad configuration in ramstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config override_gpio_table_extend[] = { + + /* Configure the WWAN GPIO pads */ + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the WLAN GPIO pads */ + /* D7 : WLAN_CLKREQ_ODL */ + PAD_NC(GPP_D7, NONE), + /* H3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + + /* Configure the SSD GPIO pads */ + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), + /* E17 : SSD_PLN_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* F12 : GSXDOUT ==> WWAN_RST_L */ @@ -67,25 +119,85 @@ PAD_CFG_GPO(GPP_H13, 1, DEEP), };
+/* Early pad configuration in bootblock for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config early_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + static const struct pad_config romstage_gpio_table[] = { /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), };
+ +/* Pad configuration in romstage for craaskneo/craaskino, board id >= 0x20 */ +static const struct pad_config romstage_gpio_table_extend[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(override_gpio_table_extend); + return override_gpio_table_extend; + } + *num = ARRAY_SIZE(override_gpio_table); return override_gpio_table; }
const struct pad_config *variant_early_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(early_gpio_table_extend); + return early_gpio_table_extend; + } + *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; }
const struct pad_config *variant_romstage_gpio_table(size_t *num) { + const uint32_t id = board_id(); + + if (id >= 0x20) { + *num = ARRAY_SIZE(romstage_gpio_table_extend); + return romstage_gpio_table_extend; + } + *num = ARRAY_SIZE(romstage_gpio_table); return romstage_gpio_table; } diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 6db23d4..db9e363 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -444,6 +444,14 @@ end probe SD_CARD SD_GL9750S end + device ref pcie_rp9 on + # Enable NVMe SSD PCIe 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0]
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Ren Kuo (Code Review)