[XS] Change in coreboot[main]: soc/{intel,amd}/gpio: Correct SOC GPIO OP

[Sean Rhodes (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier.

Hello Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86399?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/{intel,amd}/gpio: Correct SOC GPIO OP
......................................................................

soc/{intel,amd}/gpio: Correct SOC GPIO OP

The current use of `acpigen_write_integer` called via
`acpigen_soc_get_tx_gpio` will produce the below:
```
    0x6E = _SB.PCI0.GTXS /* External reference */
    Local0
```
This does not work, as it includes the byte prefix.

Change it to use `acpigen_emit_integer`, so that it produces:
```
    Local0 = GTXS (0x6E)
```

This fixes an issue in Device Manager on Windows where devices
report a power failure.

Test=build and boot various starlabs boards, dump SSDT and
verify it's correct.

Change-Id: Id03d7ca0e328917fc8379adb967a2a122c7ff85f
Signed-off-by: Sean Rhodes 
---
M src/soc/amd/common/block/acpi/gpio.c
M src/soc/intel/common/block/acpi/gpio.c
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/86399/2