Change in coreboot[master]: soc/fsp_baytrail: Fix vboot and TPM support

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/23798

Change subject: soc/fsp_baytrail: Fix vboot and TPM support
......................................................................

soc/fsp_baytrail: Fix vboot and TPM support

* Add default for VBOOT_STARTS_IN_* romstage.
* Remove unecessary TPM ACPI code which is normally
  done inside the tpm driver itself.

Change-Id: Id33b7f2b9269593cd3e62f63752a660a144600da
Signed-off-by: Philipp Deppenwiese 
---
M src/soc/intel/fsp_baytrail/Kconfig
M src/soc/intel/fsp_baytrail/acpi/lpc.asl
2 files changed, 3 insertions(+), 23 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/23798/1

diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 549ea55..601767b 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -47,6 +47,9 @@
    # Microcode header files are delivered in FSP package
    select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN

+config VBOOT
+	select VBOOT_STARTS_IN_ROMSTAGE
+
 config SOC_INTEL_FSP_BAYTRAIL_MD
    bool
    default n
diff --git a/src/soc/intel/fsp_baytrail/acpi/lpc.asl b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
index 17d6f43..00aac51 100644
--- a/src/soc/intel/fsp_baytrail/acpi/lpc.asl
+++ b/src/soc/intel/fsp_baytrail/acpi/lpc.asl
@@ -135,27 +135,4 @@

// Include mainboard's superio.asl file.
    #include "acpi/superio.asl"
-
-#if IS_ENABLED(CONFIG_LPC_TPM)
-	Device (TPM)		// Trusted Platform Module
-	{
-		Name(_HID, EISAID("IFX0102"))
-		Name(_CID, 0x310cd041)
-		Name(_UID, 1)
-
-		Method(_STA, 0)
-		{
-			If (TPMP) {
-				Return (0xf)
-			}
-			Return (0x0)
-		}
-
-		Name(_CRS, ResourceTemplate() {
-			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
-			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
-			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
-		})
-	}
-#endif
 }