Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44728
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,245 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e3463cd..2b9e0d6 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -17,7 +17,7 @@
romstage-y += ../common/cbmem.c romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c -romstage-y += dramc_subsys_config.c dramc_ana_init_config.c +romstage-y += dramc_subsys_config.c dramc_ana_init_config.c dramc_dig_config.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_dig_config.c b/src/soc/mediatek/mt8192/dramc_dig_config.c new file mode 100644 index 0000000..c13f24c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_dig_config.c @@ -0,0 +1,1241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +static void dig_phy_config(dramc_subsys_config *subsys) +{ + u8 rk_swap_en = 0; + + dramc_dbg("[Flow] Enable top DCM control\n"); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_IDLE_FSEL, 3); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 0, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_APB_SEL, 0x17, + MISC_CG_CTRL2_RG_MEM_DCM_APB_TOG, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl0, + MISC_CTRL0_R_STBENCMP_DIV4CK_EN, 0, + MISC_CTRL0_R_DQS0IEN_DIV4_CK_CG_CTRL, 1, + MISC_CTRL0_R_DQS1IEN_DIV4_CK_CG_CTRL, 1, + MISC_CTRL0_R_CLKIEN_DIV4_CK_CG_CTRL, 0, + MISC_CTRL0_R_DMSHU_PHYDCM_FORCEOFF, 1); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_rxdvs2, + MISC_RXDVS2_R_DMRXDVS_SHUFFLE_CTRL_CG_IG, 1); + + dramc_dbg("Enable DLL master slave shuffle \n"); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dvfs_emi_clk, + MISC_DVFS_EMI_CLK_RG_DLL_SHUFFLE_DDRPHY, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_RK_PINMUXSWAP_EN, rk_swap_en); + + udelay(1); + + if (subsys->a_cfg->rank_mode==0) { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 4, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 4, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq10, + B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq10, + B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 0); + } else { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq10, + B0_DQ10_ARPI_CG_RK1_SRC_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq10, + B1_DQ10_ARPI_CG_RK1_SRC_SEL_B1, 1); + } + + if (subsys->a_cfg->new_8x_mode==1) { + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_SHUFFLE_PI_RESET_ENABLE, 1, + MISC_DVFSCTL_R_DVFS_MCK8X_MARGIN, 3); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + } +} + +static void gating_mode_cfg(dramc_subsys_config *subsys) +{ + struct gating_config *gat_c = subsys->gat_c; + + gat_c->gat_track_en = ((subsys->dvfs_core->dq_semi_open == 1) + ||(subsys->dvfs_core->dq_ca_open==1)) ? 0 : 1; + gat_c->rx_gating_mode = 2; + gat_c->rx_gating_track_mode = 2; + gat_c->valid_lat_value = 1; +} + +static void dphy_gat_track_config(dramc_subsys_config *subsys) +{ + dramc_dbg("Enter into Gating configuration\n"); + u8 selph_mode = 1; + struct gating_config *gat_c = subsys->gat_c; + + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_STBCNT_SW_RST, !gat_c->gat_track_en); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, selph_mode); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_STBCNT_SHU_RST_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_DIS_PI_TRACK_AS_NOT_RD, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_OP_BIAS_SW_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_PICG_EARLY_1T_EN, 1); + + switch (gat_c->rx_gating_mode) { + case 0: + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DQSIEN_BURST_MODE, 0); + break; + case 1: + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 1); + break; + case 2: + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 2); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_DQSIEN_7UI_EN, 1); + break; + case 3: + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_BIAS_VREF_SEL_B1, 0); + break; + default: + dramc_dbg("ERROR: Gating Mode choose unexpected Mode!!!!\n"); + break; + } + + if (gat_c->rx_gating_track_mode == 2) { + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal, + MISC_STBCAL_STB_DQIEN_IG, 1, + MISC_STBCAL_PICHGBLOCK_NORD, 1, + MISC_STBCAL_REFUICHG, 0, + MISC_STBCAL_PHYVALID_IG, 0, + MISC_STBCAL_STBSTATE_OPT, 0, + MISC_STBCAL_STBDLELAST_FILTER, 0, + MISC_STBCAL_STBDLELAST_PULSE, 0, + MISC_STBCAL_STBDLELAST_OPT, 0, + MISC_STBCAL_PIMASK_RKCHG_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal1, + MISC_STBCAL1_STBCAL_FILTER, 1, + MISC_STBCAL1_STB_FLAGCLR_OPT, 1, + MISC_STBCAL1_STB_SHIFT_DTCOUT_IG, 1, + MISC_STBCAL1_STBCNT_MODESEL, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl0, + MISC_CTRL0_R_DMDQSIEN_FIFO_EN, 1, + MISC_CTRL0_R_DMVALID_DLY, 0, + MISC_CTRL0_R_DMVALID_DLY_OPT, 0, + MISC_CTRL0_R_DMSTBEN_SYNCOPT, 0, + MISC_CTRL0_R_DMVALID_NARROW_IG, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq6, + B0_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 1+gat_c->valid_lat_value, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0+gat_c->valid_lat_value); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq6, + B1_DQ6_RG_RX_ARDQ_DMRANK_OUTSEL_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 1+gat_c->valid_lat_value, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0+gat_c->valid_lat_value); + } + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_phy2, + B0_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_phy2, + B1_PHY2_RG_RX_ARDQS_DQSIEN_UI_LEAD_LAG_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal, + MISC_STBCAL_DQSIENMODE, 1, + MISC_STBCAL_SREF_DQSGUPD, 1, + MISC_STBCAL_DQSIENCG_CHG_EN, 1, + MISC_STBCAL_PICGEN, 1, + MISC_STBCAL_RKCHGMASKDIS, 0, + MISC_STBCAL_STBCAL2R, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMDQSIENCG_EN, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_GERRSTOP, 0, + MISC_STBCAL2_STB_GERR_RST, 0, + MISC_STBCAL2_STB_GERR_B01, 1, + MISC_STBCAL2_STB_GERR_B23, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_gate_en_ctrl, + MISC_RX_IN_GATE_EN_CTRL_RX_IN_GATE_EN_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rx_in_buff_en_ctrl, + MISC_RX_IN_BUFF_EN_CTRL_RX_IN_BUFF_EN_OPT, 1); + + if (subsys->a_cfg->rank_mode == 1) + SET32_BITFIELDS(&ch[0].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_IG_XRANK_CG_RST, 1, + MISC_STBCAL2_STB_RST_BY_RANK, 1, + MISC_STBCAL2_DQSIEN_SELPH_BY_RANK_EN, 1); + dramc_dbg("Exit from Gating configuration\n"); +} + +static void dig_config_shuf_alg_txca(dram_freq_grp freq_group) +{ + dramc_dbg("[TX_CA][Delay]\n"); + + u8 tx_ui = (freq_group <= DDRFREQ_400) ? 1: 0 ; + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca1, + SHU_SELPH_CA1_TXDLY_CS, 0, + SHU_SELPH_CA1_TXDLY_CKE, 0, + SHU_SELPH_CA1_TXDLY_ODT, 0, + SHU_SELPH_CA1_TXDLY_RESET, 0, + SHU_SELPH_CA1_TXDLY_WE, 0, + SHU_SELPH_CA1_TXDLY_CAS, 0, + SHU_SELPH_CA1_TXDLY_RAS, 0, + SHU_SELPH_CA1_TXDLY_CS1, 0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca2, + SHU_SELPH_CA2_TXDLY_BA0, 0, + SHU_SELPH_CA2_TXDLY_BA1, 0, + SHU_SELPH_CA2_TXDLY_BA2, 0, + SHU_SELPH_CA2_TXDLY_CKE1, 0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca3, + SHU_SELPH_CA3_TXDLY_RA0, 0, + SHU_SELPH_CA3_TXDLY_RA1, 0, + SHU_SELPH_CA3_TXDLY_RA2, 0, + SHU_SELPH_CA3_TXDLY_RA3, 0, + SHU_SELPH_CA3_TXDLY_RA4, 0, + SHU_SELPH_CA3_TXDLY_RA5, 0, + SHU_SELPH_CA3_TXDLY_RA6, 0, + SHU_SELPH_CA3_TXDLY_RA7, 0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca4, + SHU_SELPH_CA4_TXDLY_RA8, 0, + SHU_SELPH_CA4_TXDLY_RA9, 0, + SHU_SELPH_CA4_TXDLY_RA10, 0, + SHU_SELPH_CA4_TXDLY_RA11, 0, + SHU_SELPH_CA4_TXDLY_RA12, 0, + SHU_SELPH_CA4_TXDLY_RA13, 0, + SHU_SELPH_CA4_TXDLY_RA14, 0, + SHU_SELPH_CA4_TXDLY_RA15, 0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca5, + SHU_SELPH_CA5_DLY_CS, tx_ui, + SHU_SELPH_CA5_DLY_CKE, 1, + SHU_SELPH_CA5_DLY_ODT, 0, + SHU_SELPH_CA5_DLY_RESET, 1, + SHU_SELPH_CA5_DLY_WE, 1, + SHU_SELPH_CA5_DLY_CAS, 1, + SHU_SELPH_CA5_DLY_RAS, 1, + SHU_SELPH_CA5_DLY_CS1, tx_ui); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca6, + SHU_SELPH_CA6_DLY_BA0, 1, + SHU_SELPH_CA6_DLY_BA1, 1, + SHU_SELPH_CA6_DLY_BA2, 1, + SHU_SELPH_CA6_DLY_CKE1, 1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca7, + SHU_SELPH_CA7_DLY_RA0, tx_ui, + SHU_SELPH_CA7_DLY_RA1, tx_ui, + SHU_SELPH_CA7_DLY_RA2, tx_ui, + SHU_SELPH_CA7_DLY_RA3, tx_ui, + SHU_SELPH_CA7_DLY_RA4, tx_ui, + SHU_SELPH_CA7_DLY_RA5, tx_ui, + SHU_SELPH_CA7_DLY_RA6, tx_ui, + SHU_SELPH_CA7_DLY_RA7, tx_ui); + SET32_BITFIELDS(&ch[0].ao.shu_selph_ca8, + SHU_SELPH_CA8_DLY_RA8, tx_ui, + SHU_SELPH_CA8_DLY_RA9, tx_ui, + SHU_SELPH_CA8_DLY_RA10, tx_ui, + SHU_SELPH_CA8_DLY_RA11, tx_ui, + SHU_SELPH_CA8_DLY_RA12, tx_ui, + SHU_SELPH_CA8_DLY_RA13, tx_ui, + SHU_SELPH_CA8_DLY_RA14, tx_ui, + SHU_SELPH_CA8_DLY_RA15, tx_ui); +} + +static void dig_config_shuf_imp(dram_freq_grp freq_group) +{ + dramc_dbg("[IMPDANCE][Configuration]\n"); + u8 ipm_odt_en; + u8 chk_cycle = 7; + u8 tx_dly_cmd = 8; + + ipm_odt_en = (freq_group > DDRFREQ_1200) ? 1 : 0; + if (freq_group >= DDRFREQ_2133) + tx_dly_cmd = 0xc; + else if (freq_group >= DDRFREQ_1600) + tx_dly_cmd = 0xa; + + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, !ipm_odt_en); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPCAL_CHKCYCLE, chk_cycle, + SHU_MISC_IMPCAL1_IMPCAL_CALICNT, 8, + SHU_MISC_IMPCAL1_IMPCAL_CALEN_CYCLE, 4, + SHU_MISC_IMPCAL1_IMPCALCNT, 0x40); + SET32_BITFIELDS(&ch[0].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_REV, ipm_odt_en?0x1b:0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_CMD2_ODTN_UPD_DIS, 1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_drving6, + SHU_MISC_DRVING6_IMP_TXDLY_CMD, tx_dly_cmd); +} + +static void dig_config_shuf_rxinput(void) +{ + u8 perbyte_track_en = 1; + u8 dqm_track_en = 1; + u8 dqm_flow_dq_sel = 3; + u8 rx_force_upd = 0; + + dramc_dbg("[RX_INPUT][Configuration] \n"); + if (rx_force_upd == 1) { + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 1); + } + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, perbyte_track_en, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, dqm_flow_dq_sel, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, dqm_track_en, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, dqm_track_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, perbyte_track_en, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, dqm_flow_dq_sel, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, dqm_track_en, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, dqm_track_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq11, + SHU_B0_DQ11_RG_RX_ARDQ_DVS_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq11, + SHU_B1_DQ11_RG_RX_ARDQ_DVS_EN_B1, 1); +} + +static void dig_config_shuf_misc_fix(const struct ddr_cali *cali, dramc_subsys_config *subsys) +{ + u8 picg_mode = 1; + u8 dqsien_dqsstb_mode=0; + u8 cas_mode = 1; + u8 wck_dual = 0; + u8 rank_mode = 1; + u8 dual_schen = 1; + u8 dqoe_opt = 0, dqoe_cnt = 0; + u32 data_rate = subsys->dfs_gp->data_rate; + struct gating_config *gat_c = subsys->gat_c; + + dramc_dbg("[DIG_SHUF_CONFIG] MISC\n"); + dual_schen = (subsys->dvfs_core->dq_p2s_ratio==4) ? 0 : 1; + + switch(subsys->dfs_gp->dqsien_mode) { + case 1: + dqsien_dqsstb_mode = 1; + break; + case 2: + dqsien_dqsstb_mode = 2; + break; + case 3: + dqsien_dqsstb_mode = 3; + break; + case 6: + dqsien_dqsstb_mode = 2; + break; + case 7: + dqsien_dqsstb_mode = 3; + break; + default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected subsys->dfs_gp->dqsien_mode=%1d \n", + subsys->dfs_gp->dqsien_mode); + break; + } + + switch(cas_mode) { + case 1: + wck_dual = 0; + break; + case 2: + wck_dual = 1; + break; + case 3: + wck_dual = 0; + break; + default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected cas_mode(%d) input\n",cas_mode); + break; + } + + SET32_BITFIELDS(&ch[0].ao.shu_common0, + SHU_COMMON0_BL4, 1, + SHU_COMMON0_FREQDIV4, subsys->dvfs_core->dq_p2s_ratio==8, + SHU_COMMON0_FDIV2, subsys->dvfs_core->dq_p2s_ratio==4, + SHU_COMMON0_BC4OTF, 1, + SHU_COMMON0_DM64BITEN, !(subsys->dvfs_core->dq_p2s_ratio==4)); + SET32_BITFIELDS(&ch[0].ao.shu_actiming_conf, + SHU_ACTIMING_CONF_TREFBWIG, 1, + SHU_ACTIMING_CONF_SCINTV, 54); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_FASTWAKE2, 1, + SHU_DCM_CTRL0_FASTWAKE, 1); + SET32_BITFIELDS(&ch[0].ao.shu_conf0, + SHU_CONF0_ADVPREEN, 1, + SHU_CONF0_DMPGTIM, 63, + SHU_CONF0_REFTHD, 0, + SHU_CONF0_PBREFEN, 1); + SET32_BITFIELDS(&ch[0].ao.shu_matype, + SHU_MATYPE_MATYPE, 2); + SET32_BITFIELDS(&ch[0].ao.shu_scheduler, + SHU_SCHEDULER_DUALSCHEN, dual_schen); + SET32_BITFIELDS(&ch[0].ao.tx_set0, + TX_SET0_WPRE2T, 1); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, + SHU_TX_SET0_WDATRGO, subsys->dvfs_core->dq_p2s_ratio == 4, + SHU_TX_SET0_WPST1P5T, data_rate >= 3200, + SHU_TX_SET0_DQOE_OPT, dqoe_opt, + SHU_TX_SET0_DQOE_CNT, dqoe_cnt, + SHU_TX_SET0_OE_EXT2UI, 0, + SHU_TX_SET0_TXUPD_W2R_SEL, + ((data_rate == 1600) && (subsys->dvfs_core->dq_p2s_ratio == 8)) ? 5 : 2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal1, + MISC_SHU_STBCAL1_STB_PI_TRACKING_RATIO, 0x30, + MISC_SHU_STBCAL1_STB_UPDMASK_EN, 1, + MISC_SHU_STBCAL1_STB_UPDMASKCYC, 9, + MISC_SHU_STBCAL1_DQSINCTL_PRE_SEL, data_rate > 1600); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, gat_c->gat_track_en, + MISC_SHU_STBCAL_STB_SELPHCALEN, gat_c->gat_track_en, + MISC_SHU_STBCAL_DQSIEN_DQSSTB_MODE, dqsien_dqsstb_mode); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_DMSTBLAT, + (((gat_c->gat_track_en) && (data_rate >= 1866)) ? + (2 + gat_c->valid_lat_value) : (gat_c->valid_lat_value)), + MISC_SHU_STBCAL_PICGLAT, 1, + MISC_SHU_STBCAL_DQSG_MODE, 1, + MISC_SHU_STBCAL_DQSIEN_PICG_MODE, picg_mode); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, picg_mode); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 1); + for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[rk].misc_shu_rk_dqsien_picg_ctrl, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_HEAD_EXT_LAT, 0, + MISC_SHU_RK_DQSIEN_PICG_CTRL_DQSIEN_PICG_TAIL_EXT_LAT, + subsys->dvfs_core->dq_p2s_ratio == 4); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_EN, 1, + MISC_SHU_RODTENSTB_RODTEN_P1_ENABLE, 0, + MISC_SHU_RODTENSTB_RODTENSTB_SELPH_MODE, rank_mode?1:picg_mode, + MISC_SHU_RODTENSTB_RODTENSTB_TRACK_UDFLWCTRL, 1, + MISC_SHU_RODTENSTB_RODTENSTB_MCK_OFFSET, + (subsys->dvfs_core->dq_p2s_ratio == 4) ? 2 : 0, + MISC_SHU_RODTENSTB_RODTENSTB__UI_OFFSET, + (subsys->dvfs_core->dq_p2s_ratio == 4) ? 1 : 4, + MISC_SHU_RODTENSTB_RODTENSTB_EXT, + (subsys->dvfs_core->dq_p2s_ratio == 16) ? + 19 : ((subsys->dvfs_core->dq_p2s_ratio == 8) ? 13 : 10)); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb1, + MISC_SHU_RODTENSTB1_RODTENCGEN_TAIL, (data_rate >= 3200) ? 1 : 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rodtenstb1, + MISC_SHU_RODTENSTB1_RODTENCGEN_HEAD, (data_rate >= 3200) ? 2 : 1); + + switch (subsys->dvfs_core->dq_p2s_ratio) { + case 4: + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 0, + MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat1, + MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 1, + MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 1, + MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 0); + break; + case 8: + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 1, + MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat1, + MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0, + MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 0, + MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 0); + break; + case 16: + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_DQSIEN_SELPH_SERMODE, 3); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rx_selph_mode, + MISC_SHU_RX_SELPH_MODE_RODT_SELPH_SERMODE, 2, + MISC_SHU_RX_SELPH_MODE_RANK_SELPH_SERMODE, 2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat1, + MISC_SHU_RDAT1_R_DMRDSEL_DIV2_OPT, 0, + MISC_SHU_RDAT1_R_DMRDSEL_LOBYTE_OPT, 0, + MISC_SHU_RDAT1_R_DMRDSEL_HIBYTE_OPT, 0); + break; + default:dramc_dbg("ERROR:Unexcepted subsys->dvfs_core.dq_p2s_ratio = %d\n", + subsys->dvfs_core->dq_p2s_ratio); + break; + } + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_cke_ctrl, + SHURK_CKE_CTRL_CKE_DBE_CNT, 0); +} + +static void dig_config_shuf_misc_dqsgretry(dram_freq_grp freq_group) +{ + bool is_high_speed = (freq_group == DDRFREQ_2133); + + dramc_dbg("[DIG_SHUF_CONFIG] DQSG_RETRY\n"); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_dqsg_retry1, + MISC_SHU_DQSG_RETRY1_RETRY_SW_RESET, 0, + MISC_SHU_DQSG_RETRY1_RETRY_SW_EN, 0, + MISC_SHU_DQSG_RETRY1_RETRY_DDR1866_PLUS, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_ONCE, 0, + MISC_SHU_DQSG_RETRY1_RETRY_3TIMES, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_1RANK, 0, + MISC_SHU_DQSG_RETRY1_RETRY_BY_RANK, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_DM4BYTE, 0, + MISC_SHU_DQSG_RETRY1_RETRY_DQSIENLAT, 0, + MISC_SHU_DQSG_RETRY1_RETRY_STBENCMP_ALLBYTE, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_dqsg_retry1, + MISC_SHU_DQSG_RETRY1_XSR_DQSG_RETRY_EN, 0, + MISC_SHU_DQSG_RETRY1_XSR_RETRY_SPM_MODE, 0, + MISC_SHU_DQSG_RETRY1_RETRY_CMP_DATA, 0, + MISC_SHU_DQSG_RETRY1_RETRY_ALE_BLOCK_MASK, 0, + MISC_SHU_DQSG_RETRY1_RETRY_RDY_SEL_DLE, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_USE_NON_EXTEND, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_USE_CG_GATING, is_high_speed, + MISC_SHU_DQSG_RETRY1_RETRY_ROUND_NUM, 1, + MISC_SHU_DQSG_RETRY1_RETRY_RANKSEL_FROM_PHY, 0, + MISC_SHU_DQSG_RETRY1_RETRY_PA_DISABLE, 0, + MISC_SHU_DQSG_RETRY1_RETRY_STBEN_RESET_MSK, 0, + MISC_SHU_DQSG_RETRY1_RETRY_USE_BURST_MODE, is_high_speed); +} + +static void dig_config_shuf_dbi(dramc_subsys_config *subsys) +{ + u8 rd_dbi_en = 0, wr_dbi_en = 0; + dramc_dbg("[DIG_SHUF_CONFIG] DBI\n"); + + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, rd_dbi_en, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, rd_dbi_en); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, rd_dbi_en, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, rd_dbi_en); + SET32_BITFIELDS(&ch[0].ao.shu_tx_set0, + SHU_TX_SET0_DBIWR, wr_dbi_en); +} + +static void dig_config_shuf_dvfswlrl(dramc_subsys_config *subsys) +{ + dram_config *lp4_init = subsys->lp4_init; + + u8 hwset_mr13_op_value =0; + u8 hwset_vrcg_op_value =0; + u8 hwset_mr2_op_value =0; + + dramc_dbg("[DIG_SHUF_CONFIG] DVFSRLWL\n"); + + hwset_mr13_op_value = ((lp4_init->work_fsp & 1) << 7) | + ((lp4_init->work_fsp & 1) << 6) | (( 0 << 5) | 8); + hwset_vrcg_op_value = ((lp4_init->work_fsp & 1) << 7) | + ((lp4_init->work_fsp & 1) << 6); + hwset_mr2_op_value = ((lp4_init->mr_wl & 7) << 3) | (lp4_init->mr_wl & 7); + + SET32_BITFIELDS(&ch[0].ao.shu_hwset_mr13, + SHU_HWSET_MR13_HWSET_MR13_OP, hwset_mr13_op_value); + SET32_BITFIELDS(&ch[0].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_HWSET_VRCG_OP, hwset_vrcg_op_value); + SET32_BITFIELDS(&ch[0].ao.shu_hwset_vrcg, + SHU_HWSET_VRCG_VRCGDIS_PRDCNT, 0xb); + SET32_BITFIELDS(&ch[0].ao.shu_hwset_mr2, + SHU_HWSET_MR2_HWSET_MR2_OP, hwset_mr2_op_value); +} + +static void dig_config_dvfs_dependence(dramc_subsys_config *subsys) +{ + dig_config_shuf_dvfswlrl(subsys); + + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_dvfsdll, + MISC_SHU_DVFSDLL_R_DLL_IDLE, 0x37, + MISC_SHU_DVFSDLL_R_2ND_DLL_IDLE, 0x4d, + MISC_SHU_DVFSDLL_R_BYPASS_1ST_DLL, subsys->a_cfg->all_slave_en, + MISC_SHU_DVFSDLL_R_BYPASS_2ND_DLL, 0); +} + +static void dramc_common_config(const struct ddr_cali *cali, + dramc_subsys_config *subsys) +{ + u8 rd2mrr_extend_en = 1; + u8 ebg_en = 0; + u8 tmrri_mode = 1; + u8 noblock_ale_en = 1; + u8 runtime_mrr = 1; + u8 pinmux = get_pinmux_type(cali); + + SET32_BITFIELDS(&ch[0].ao.ddrcommon0, + DDRCOMMON0_BK8EN, 1, + DDRCOMMON0_LPDDR5EN, 0, + DDRCOMMON0_LPDDR4EN, 1, + DDRCOMMON0_TRCDEARLY, 0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DMPINMUX, pinmux); + SET32_BITFIELDS(&ch[0].ao.rx_set0, + RX_SET0_DM4TO1MODE, 0); + SET32_BITFIELDS(&ch[0].ao.refctrl0, + REFCTRL0_REF_PREGATE_CNT, 5, + REFCTRL0_DMPGVLD_IG, 0, + REFCTRL0_DISBYREFNUM, 4, + REFCTRL0_PBREF_DISBYRATE, 0, + REFCTRL0_PBREF_DISBYREFNUM, 1, + REFCTRL0_PBREF_BK_REFA_ENA, 1, + REFCTRL0_PBREF_BK_REFA_NUM, 1); + SET32_BITFIELDS(&ch[0].ao.refctrl1, + REFCTRL1_PB2AB_OPT, 1, + REFCTRL1_REF_QUE_AUTOSAVE_EN, 1, + REFCTRL1_REF_OVERHEAD_ALL_REFPB_ENA, 0, + REFCTRL1_REF_OVERHEAD_SLOW_REFPB_ENA, 1, + REFCTRL1_REF_OVERHEAD_ALL_REFAL_ENA, 0, + REFCTRL1_REF_OVERHEAD_SLOW_REFAL_ENA, 0, + REFCTRL1_REF_OVERHEAD_RATE_REFPB_ENA, 0, + REFCTRL1_REF_OVERHEAD_RATE_REFAL_ENA, 0); + SET32_BITFIELDS(&ch[0].ao.refctrl2, + REFCTRL2_REF_OVERHEAD_RATE, 0); + SET32_BITFIELDS(&ch[0].ao.dllfrz_ctrl, + DLLFRZ_CTRL_UPDBYWR, 0, + DLLFRZ_CTRL_DLLFRZ, 1); + SET32_BITFIELDS(&ch[0].ao.dramctrl, + DRAMCTRL_ADRDECEN, 0, + DRAMCTRL_PREALL_OPTION, 1, + DRAMCTRL_REQQUE_THD_EN, 1, + DRAMCTRL_DYNMWREN, 1, + DRAMCTRL_AG0MWR, 0, + DRAMCTRL_ADRBIT3DEC, 0, + DRAMCTRL_CTOREQ_HPRI_OPT, 0); + SET32_BITFIELDS(&ch[0].ao.actiming_ctrl, + ACTIMING_CTRL_CLKWITRFC, 0, + ACTIMING_CTRL_SEQCLKRUN3, 1, + ACTIMING_CTRL_FASTW2R, 0, + ACTIMING_CTRL_REFBW_FREN, 0, + ACTIMING_CTRL_TMRRICHKDIS, 1, + ACTIMING_CTRL_REFNA_OPT, 0, + ACTIMING_CTRL_MRRIOPT, !tmrri_mode, + ACTIMING_CTRL_TMRRIBYRK_DIS, !tmrri_mode, + ACTIMING_CTRL_TMRRICHKDIS, tmrri_mode); + SET32_BITFIELDS(&ch[0].ao.arbctl, + ARBCTL_MAXPENDCNT, 0x80, + ARBCTL_WDATACNTDIS, 0); + SET32_BITFIELDS(&ch[0].ao.dram_clk_ctrl, + DRAM_CLK_CTRL_CLK_EN, 1); + SET32_BITFIELDS(&ch[0].ao.clkar, + CLKAR_DCMREF_OPT, 1); + SET32_BITFIELDS(&ch[0].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_COMBCLKCTRL, 1, + DRAMC_PD_CTRL_MIOCKCTRLOFF, 0, + DRAMC_PD_CTRL_PHYCLKDYNGEN, 1, + DRAMC_PD_CTRL_DCMEN, 1, + DRAMC_PD_CTRL_DCMEN2, 1, + DRAMC_PD_CTRL_PG_DCM_OPT, 0); + SET32_BITFIELDS(&ch[0].ao.rkcfg, + RKCFG_CKE2RANK, 0, + RKCFG_MRS2RK, 0); + SET32_BITFIELDS(&ch[0].ao.ckectrl, + CKECTRL_CKE2RANK_OPT2, 1, + CKECTRL_CKEON, 1, + CKECTRL_CKETIMER_SEL, 0, + CKECTRL_CKE2RANK_OPT8, 1, + CKECTRL_RUNTIMEMRRMIODIS, !runtime_mrr, + CKECTRL_FASTWAKE_SEL, 1, + CKECTRL_CKEPBDIS, 1, + CKECTRL_RUNTIMEMRRCKEFIX, !tmrri_mode, + CKECTRL_CKELCKFIX, 0); + SET32_BITFIELDS(&ch[0].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_SELFREF_AUTOSAVE_EN, 1, + SREF_DPD_CTRL_GT_SYNC_MASK, 0, + SREF_DPD_CTRL_DAT_SYNC_MASK, 0, + SREF_DPD_CTRL_PHY_SYNC_MASK, 0, + SREF_DPD_CTRL_LPSM_BYPASS_B, 1, + SREF_DPD_CTRL_SREF_PRD_OPT, 0, + SREF_DPD_CTRL_CLR_EN, 1, + SREF_DPD_CTRL_SRFPD_DIS, 0, + SREF_DPD_CTRL_SREFDLY, 8, + SREF_DPD_CTRL_SREF_HW_EN, 1); + SET32_BITFIELDS(&ch[0].ao.scheduler_com, + SCHEDULER_COM_DISRDPHASE1, 1, + SCHEDULER_COM_MWHPRIEN, 1, + SCHEDULER_COM_RWHPRICTL, 0, + SCHEDULER_COM_RWOFOEN, 1, + SCHEDULER_COM_RWSPLIT, 1); + SET32_BITFIELDS(&ch[0].ao.perfctl0, + PERFCTL0_EMILLATEN, 1, + PERFCTL0_RWHPRIEN, 1, + PERFCTL0_EBG_EN, ebg_en, + PERFCTL0_RWLLATEN, 1, + PERFCTL0_RWAGEEN, 1, + PERFCTL0_WFLUSHEN, 1, + PERFCTL0_REORDEREN, 0, + PERFCTL0_REORDER_MODE, 0); + SET32_BITFIELDS(&ch[0].ao.hw_mrr_fun, + HW_MRR_FUN_TMRR_ENA, runtime_mrr, + HW_MRR_FUN_TRPMRR_EN, 0, + HW_MRR_FUN_TRCDMRR_EN, 0, + HW_MRR_FUN_MRR_HW_HIPRI, 1, + HW_MRR_FUN_TR2MRR_ENA, rd2mrr_extend_en, + HW_MRR_FUN_R2MRRHPRICTL, rd2mrr_extend_en, + HW_MRR_FUN_MANTMRR_EN, rd2mrr_extend_en); + SET32_BITFIELDS(&ch[0].ao.zq_set0, + ZQ_SET0_ZQCSAD, 0x0a, + ZQ_SET0_ZQCSOP, 0x56); + SET32_BITFIELDS(&ch[0].ao.mpc_option, + MPC_OPTION_MPCRKEN, 1); + SET32_BITFIELDS(&ch[0].ao.mpc_ctrl, + MPC_CTRL_REFR_BLOCKEN, !runtime_mrr, + MPC_CTRL_ZQ_BLOCKALE_OPT, noblock_ale_en, + MPC_CTRL_MPC_BLOCKALE_OPT, noblock_ale_en, + MPC_CTRL_MPC_BLOCKALE_OPT1, noblock_ale_en, + MPC_CTRL_MPC_BLOCKALE_OPT2, noblock_ale_en); + SET32_BITFIELDS(&ch[0].ao.hmr4, + HMR4_SPDR_MR4_OPT, 1); + SET32_BITFIELDS(&ch[0].ao.rk[0].rk_test2_a1, + RK_TEST2_A1_TEST2_BASE, 0x010000); + SET32_BITFIELDS(&ch[0].ao.test2_a2, + TEST2_A2_TEST2_OFF, 0x000020); + SET32_BITFIELDS(&ch[0].ao.test2_a3, + TEST2_A3_TESTAUDPAT, 1, + TEST2_A3_TEST2WREN2_HW_EN, 1); + SET32_BITFIELDS(&ch[0].ao.test2_a4, + TEST2_A4_TESTAUDINIT, 0x11, + TEST2_A4_TESTAUDINC, 0x0d, + TEST2_A4_TESTAGENTRKSEL, 0x04); + SET32_BITFIELDS(&ch[0].ao.cmd_dec_ctrl0, + CMD_DEC_CTRL0_RKMODE, 1); + SET32_BITFIELDS(&ch[0].ao.misctl0, + MISCTL0_PAGDIS, 0, + MISCTL0_PBC_ARB_E1T, 0, + MISCTL0_REFA_ARB_EN2, 1, + MISCTL0_PBC_ARB_EN, 1, + MISCTL0_REFP_ARB_EN2, 1, + MISCTL0_EMIPREEN, 0, + MISCTL0_PG_WAKEUP_OPT, 1); + SET32_BITFIELDS(&ch[0].ao.scsmctrl, + SCSMCTRL_SC_PG_MAN_DIS, 1, + SCSMCTRL_SC_PG_UPD_OPT, tmrri_mode); + SET32_BITFIELDS(&ch[0].ao.shuctrl1, + SHUCTRL1_FC_PRDCNT, 0x1a); + SET32_BITFIELDS(&ch[0].ao.dvfs_timing_ctrl1, + DVFS_TIMING_CTRL1_DMSHU_CNT, 1); + SET32_BITFIELDS(&ch[0].ao.refpend1, + REFPEND1_MPENDREFCNT_TH0, 0x5, + REFPEND1_MPENDREFCNT_TH1, 0x5, + REFPEND1_MPENDREFCNT_TH2, 0x5, + REFPEND1_MPENDREFCNT_TH3, 0x5, + REFPEND1_MPENDREFCNT_TH4, 0x5, + REFPEND1_MPENDREFCNT_TH5, 0x3, + REFPEND1_MPENDREFCNT_TH6, 0x3, + REFPEND1_MPENDREFCNT_TH7, 0x3); + SET32_BITFIELDS(&ch[0].ao.cbt_wlev_ctrl1, + CBT_WLEV_CTRL1_CATRAIN_INTV, 0x10, + CBT_WLEV_CTRL1_CATRAINLAT, 0x3); + SET32_BITFIELDS(&ch[0].ao.tx_set0, + TX_SET0_DRSCLR_EN, 1, + TX_SET0_RK_SCINPUT_OPT, !tmrri_mode); + + if (subsys->a_cfg->aphy_comb_en == 1) + SET32_BITFIELDS(&ch[0].ao.tx_set0, TX_SET0_OE_DOWNGRADE, 1); + + SET32_BITFIELDS(&ch[0].ao.dqsoscr, + DQSOSCR_SREF_TXUI_RELOAD_OPT, 0, + DQSOSCR_SREF_TXPI_RELOAD_OPT, 1); + SET32_BITFIELDS(&ch[0].ao.dummy_rd, + DUMMY_RD_DRS_SELFWAKE_DMYRD_DIS, 1, + DUMMY_RD_RANK_NUM, 2, + DUMMY_RD_DUMMY_RD_SW, 1, + DUMMY_RD_DQSG_DMYRD_EN, 1); + SET32_BITFIELDS(&ch[0].ao.dummy_rd_intv, + DUMMY_RD_INTV_DUMMY_RD_CNT7, 0, + DUMMY_RD_INTV_DUMMY_RD_CNT6, 1, + DUMMY_RD_INTV_DUMMY_RD_CNT5, 1, + DUMMY_RD_INTV_DUMMY_RD_CNT4, 0, + DUMMY_RD_INTV_DUMMY_RD_CNT3, 1, + DUMMY_RD_INTV_DUMMY_RD_CNT2, 0, + DUMMY_RD_INTV_DUMMY_RD_CNT1, 0, + DUMMY_RD_INTV_DUMMY_RD_CNT0, 0); + SET32_BITFIELDS(&ch[0].ao.rk[0].rk_dqsosc, + RK_DQSOSC_RK0_BYTE_MODE, cali->cbt_mode[RANK_0]); + SET32_BITFIELDS(&ch[0].ao.rk[1].rk_dqsosc, + RK_DQSOSC_RK0_BYTE_MODE, cali->cbt_mode[RANK_1]); + SET32_BITFIELDS(&ch[0].ao.tx_tracking_set0, + TX_TRACKING_SET0_TX_TRACKING_OPT, 0); + SET32_BITFIELDS(&ch[0].ao.tx_cg_set0, + TX_CG_SET0_SELPH_4LCG_DIS, 1); + SET32_BITFIELDS(&ch[0].ao.tx_freq_ratio_old_mode0, + TX_FREQ_RATIO_OLD_MODE0_SHUFFLE_LEVEL_MODE_SELECT, 1); + SET32_BITFIELDS(&ch[0].ao.swcmd_ctrl1, + SWCMD_CTRL1_WRFIFO_MODE2, 1); + SET32_BITFIELDS(&ch[0].ao.dbg_cmddec_cmdsel0, + DBG_CMDDEC_CMDSEL0_RANK0_10GBEN, subsys->lp4_init->ex_row_en[0], + DBG_CMDDEC_CMDSEL0_RANK1_10GBEN, subsys->lp4_init->ex_row_en[1]); + SET32_BITFIELDS(&ch[0].ao.dbiwr_protect, + DBIWR_PROTECT_DBIWR_IMP_EN, 1, + DBIWR_PROTECT_DBIWR_PINMUX_EN, 0); + SET32_BITFIELDS(&ch[0].ao.rx_set0, + RX_SET0_PRE_DLE_VLD_OPT, 1, + RX_SET0_DATLAT_PDLE_TH, 7); + SET32_BITFIELDS(&ch[0].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_PENABLE_LAT_WR, 1, + MISC_SRAM_DMA0_KEEP_APB_ARB_ENA, 1, + MISC_SRAM_DMA0_KEEP_SRAM_ARB_ENA, 1); + SET32_BITFIELDS(&mtk_dpm->mclk_div, + SSPM_MCLK_DIV_MCLK_DCM_EN, 1); + + write32(&ch[0].phy_ao.misc_dbg_irq_ctrl1, 0xFFFFFFFF); + write32(&ch[0].phy_ao.misc_dbg_irq_ctrl4, 0xFFFFFFFF); + write32(&ch[0].phy_ao.misc_dbg_irq_ctrl7, 0xFFFFFFFF); +} + +static void dvfs_pre_config(dramc_subsys_config *subsys) +{ + u32 mcp_en = 0; + u32 ref_104m_en = 1; + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_dbg("Enter into dvfs_pre_config\n"); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[0].b0_dq11, + B0_DQ11_DMY_DQ11_B0, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.dvs_b[1].b0_dq11, + B1_DQ11_DMY_DQ11_B1, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_VRCG_EN, 1, + DVFS_CTRL0_DVFS_SYNC_MASK, 0, + DVFS_CTRL0_MR13_SHU_EN, 1, + DVFS_CTRL0_HWSET_WLRL, 1, + DVFS_CTRL0_MRWWOPRA, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_SPM_DVFS_CONTROL_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma0, + MISC_SRAM_DMA0_DMA_TIMER_EN, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_sram_dma1, + MISC_SRAM_DMA1_SPM_RESTORE_STEP_EN, 0x1ffff); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_cg_ctrl7, + MISC_CG_CTRL7_ARMCTL_CK_OUT_CG_SEL, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_DVFS_PICG_POSTPONE, 1, + MISC_DVFSCTL_R_DMSHUFFLE_CHANGE_FREQ_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_CDC_MUX_SEL_OPTION, 0, + MISC_DVFSCTL2_R_DVFS_SYNC_MODULE_RST_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 1); + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CKE_OPT, 0, + DVFS_CTRL0_SCARB_PRI_OPT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_MCLK, 0, + MISC_DVFSCTL3_RG_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 1, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_DESTI, 3, + MISC_DVFSCTL3_RG_DVFS_MEM_CK_SEL_SOURCE, 1, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 7, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_MCLK, 1, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x3f); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 1, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_AFT_CHG_TO_BCLK, 0x10); + SET32_BITFIELDS(&ch[chn].ao.dvfs_timing_ctrl1, + DVFS_TIMING_CTRL1_DMSHU_CNT, 1, + DVFS_TIMING_CTRL1_SHU_PERIOD_GO_ZERO_CNT, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_CDC_OPTION, 1, + MISC_DVFSCTL2_R_DVFS_DLL_CHA, 0, + MISC_DVFSCTL2_RG_TOPCK_FMEM_CK_BLOCK_DURING_DFS, 1, + MISC_DVFSCTL2_R_DVFS_PARK_N, 1, + MISC_DVFSCTL2_R_DVFS_OPTION, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_RG_52M_104M_SEL, ref_104m_en); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_opt, + MISC_SHU_OPT_R_DQB0_SHU_PHY_GATING_RESETB_SPM_EN, 1, + MISC_SHU_OPT_R_DQB0_SHU_PHDET_SPM_EN, 2, + MISC_SHU_OPT_R_DQB1_SHU_PHY_GATING_RESETB_SPM_EN, 1, + MISC_SHU_OPT_R_DQB1_SHU_PHDET_SPM_EN, 2, + MISC_SHU_OPT_R_CA_SHU_PHY_GATING_RESETB_SPM_EN, 1, + MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 1); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, (ref_104m_en==1)?3:1, + MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, (ref_104m_en==1)?3:1, + MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, (ref_104m_en==1)?3:1); + } + + if (subsys->a_cfg->dll_async_en == 0) { + SET32_BITFIELDS(&ch[1].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_DLL_CHA, 0); + SET32_BITFIELDS(&ch[1].phy_ao.misc_shu_opt, + MISC_SHU_OPT_R_CA_SHU_PHDET_SPM_EN, 2); + } + + if (mcp_en == 1) { + dramc_dbg("MCP Enable leading 2ch's sync singles should adjust delay margin."); + SET32_BITFIELDS(&ch[1].phy_ao.misc_dvfsctl, + MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, + (ref_104m_en==1) ? 6 : 4); + SET32_BITFIELDS(&ch[1].phy_ao.misc_dvfsctl3, + MISC_DVFSCTL3_RG_CNT_PHY_ST_DELAY_BEF_CHG_TO_BCLK, 9); + } + + SET32_BITFIELDS(&ch[0].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_FMEM_CK_MUX, 1); + SET32_BITFIELDS(&ch[0].ao.dvfs_ctrl0, + DVFS_CTRL0_R_DRAMC_CHA, 0, + DVFS_CTRL0_SHU_PHYRST_SEL, 0); + SET32_BITFIELDS(&ch[1].phy_ao.misc_ckmux_sel, + MISC_CKMUX_SEL_FMEM_CK_MUX, 3); + SET32_BITFIELDS(&ch[1].ao.dvfs_ctrl0, + DVFS_CTRL0_R_DRAMC_CHA, 0, + DVFS_CTRL0_SHU_PHYRST_SEL, 1); + dramc_set_broadcast(DRAMC_BROADCAST_ON); +} + +static void ddrphy_picg_config(void) +{ + u8 picg_mode = 1; + u8 misc_cg_en = 1; + u8 misc_cg_reverse = 0; + + dramc_dbg("Enter into PICG configuration\n"); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl4, + MISC_CTRL4_R_OPT2_MPDIV_CG, picg_mode, + MISC_CTRL4_R_OPT2_CG_MCK, picg_mode, + MISC_CTRL4_R_OPT2_CG_DQM, picg_mode, + MISC_CTRL4_R_OPT2_CG_DQS, picg_mode, + MISC_CTRL4_R_OPT2_CG_DQ, picg_mode, + MISC_CTRL4_R_OPT2_CG_DQSIEN, picg_mode); + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl3, + MISC_CTRL3_ARPI_MPDIV_CG_DQ_OPT, !picg_mode, + MISC_CTRL3_ARPI_CG_MCK_DQ_OPT, !picg_mode, + MISC_CTRL3_ARPI_CG_DQS_OPT, !picg_mode, + MISC_CTRL3_ARPI_CG_DQ_OPT, !picg_mode); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl0, + MISC_CG_CTRL0_RG_CG_DRAMC_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_COMB_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_CMD_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_COMB0_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_COMB1_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_RX_CMD_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_RX_COMB0_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_RX_COMB1_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL0_RG_CG_INFRA_OFF_DISABLE, !misc_cg_en); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl2, + MISC_CG_CTRL2_RG_MEM_DCM_CG_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL2_RG_PIPE0_CG_OFF_DISABLE, !misc_cg_en, + MISC_CG_CTRL2_RG_PHY_CG_OFF_DISABLE, !misc_cg_en); + SET32_BITFIELDS(&ch[0].phy_ao.misc_cg_ctrl5, + MISC_CG_CTRL5_R_DQ1_DLY_DCM_EN, misc_cg_en, + MISC_CG_CTRL5_R_DQ0_DLY_DCM_EN, misc_cg_en, + MISC_CG_CTRL5_R_CA_DLY_DCM_EN, misc_cg_en, + MISC_CG_CTRL5_R_DQ1_PI_DCM_EN, misc_cg_en, + MISC_CG_CTRL5_R_DQ0_PI_DCM_EN, misc_cg_en, + MISC_CG_CTRL5_R_CA_PI_DCM_EN, misc_cg_en); + + if (misc_cg_reverse == 1) { + SET32_BITFIELDS(&ch[0].ao.rx_cg_set0, + RX_CG_SET0_RDATCKAR, 1, + RX_CG_SET0_RDYCKAR, 1); + SET32_BITFIELDS(&ch[0].ao.sref_dpd_ctrl, + SREF_DPD_CTRL_CMDCKAR, 1); + SET32_BITFIELDS(&ch[0].ao.dcm_ctrl0, + DCM_CTRL0_BCLKAR, 1); + SET32_BITFIELDS(&ch[0].ao.tx_cg_set0, + TX_CG_SET0_PSELAR, 1, + TX_CG_SET0_DWCLKRUN, 1); + SET32_BITFIELDS(&ch[0].ao.scsmctrl_cg, + SCSMCTRL_CG_SCSM_CGAR, 1, + SCSMCTRL_CG_SCARB_SM_CGAR, 1); + SET32_BITFIELDS(&ch[0].ao.tx_tracking_set0, + TX_TRACKING_SET0_RDDQSOSC_CGAR, 1, + TX_TRACKING_SET0_HMRRSEL_CGAR, 1, + TX_TRACKING_SET0_TXUIPI_CAL_CGAR, 1); + SET32_BITFIELDS(&ch[0].ao.zq_set0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 1); + SET32_BITFIELDS(&ch[0].ao.actiming_ctrl, + ACTIMING_CTRL_CLKWITRFC, 1, + ACTIMING_CTRL_SEQCLKRUN3, 1, + ACTIMING_CTRL_SEQCLKRUN2, 1, + ACTIMING_CTRL_SEQCLKRUN, 1); + SET32_BITFIELDS(&ch[0].ao.clkar, + CLKAR_REQQUECLKRUN, 1, + CLKAR_REQQUE_PACG_DIS, 1); + SET32_BITFIELDS(&ch[0].ao.dramc_pd_ctrl, + DRAMC_PD_CTRL_PHYGLUECLKRUN, 1); + SET32_BITFIELDS(&ch[0].ao.test2_a3, + TEST2_A3_TESTCLKRUN, 1); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + SET32_BITFIELDS(&ch[chn].ao.dvfs_ctrl0, + DVFS_CTRL0_DVFS_CG_OPT, 1); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + SET32_BITFIELDS(&ch[0].phy_ao.misc_dutyscan1, + MISC_DUTYSCAN1_EYESCAN_DQS_OPT, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 1, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 1, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 1, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 1, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 1); + } + + dramc_dbg("Exit from PICG configuration\n"); +} + +static void io_release(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.misc_ctrl1, + MISC_CTRL1_R_DM_TX_ARCLK_OE, 1, + MISC_CTRL1_R_DM_TX_ARCMD_OE, 1); + + SET32_BITFIELDS(&ch[0].phy_ao.ca_cmd7, + CA_CMD7_RG_TX_ARCLKB_PULL_DN, 0, + CA_CMD7_RG_TX_ARCLKB_PULL_UP, 0, + CA_CMD7_RG_TX_ARCLK_PULL_DN, 0, + CA_CMD7_RG_TX_ARCLK_PULL_UP, 0, + CA_CMD7_RG_TX_ARCS0_PULL_DN, 0, + CA_CMD7_RG_TX_ARCS0_PULL_UP, 0, + CA_CMD7_RG_TX_ARCMD_PULL_DN, 0, + CA_CMD7_RG_TX_ARCMD_PULL_UP, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq7, + B0_DQ7_RG_TX_ARDQS0B_PULL_DN_B0, 0, + B0_DQ7_RG_TX_ARDQS0B_PULL_UP_B0, 0, + B0_DQ7_RG_TX_ARDQS0_PULL_DN_B0, 0, + B0_DQ7_RG_TX_ARDQS0_PULL_UP_B0, 0, + B0_DQ7_RG_TX_ARDQM0_PULL_DN_B0, 0, + B0_DQ7_RG_TX_ARDQM0_PULL_UP_B0, 0, + B0_DQ7_RG_TX_ARDQ_PULL_DN_B0, 0, + B0_DQ7_RG_TX_ARDQ_PULL_UP_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq7, + B1_DQ7_RG_TX_ARDQS0B_PULL_DN_B1, 0, + B1_DQ7_RG_TX_ARDQS0B_PULL_UP_B1, 0, + B1_DQ7_RG_TX_ARDQS0_PULL_DN_B1, 0, + B1_DQ7_RG_TX_ARDQS0_PULL_UP_B1, 0, + B1_DQ7_RG_TX_ARDQM0_PULL_DN_B1, 0, + B1_DQ7_RG_TX_ARDQM0_PULL_UP_B1, 0, + B1_DQ7_RG_TX_ARDQ_PULL_DN_B1, 0, + B1_DQ7_RG_TX_ARDQ_PULL_UP_B1, 0); +} + +static void rx_input_config(const struct ddr_cali *cali) +{ + u8 valid_lat = 1; + u8 rdsel_lat = 2; + u8 dq_min = 0; + u8 dq_max = 0xff; + u8 scale = 3; + u8 threadhold = 0; + u8 rx_force_upd = 0; + u8 f_leadlag = 0; + u8 rg_mode_en = 0; + u32 dqs_min = 0; + u32 dqs_max = 0x1ff; + + dramc_dbg("[RX_INPUT] configuration \n"); + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0, + B0_RXDVS0_R_HWSAVE_MODE_ENA_B0, 1, + B0_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B0, 0, + B0_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B0, 1, + B0_RXDVS0_R_HWRESTORE_ENA_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0, + B1_RXDVS0_R_HWSAVE_MODE_ENA_B1, 1, + B1_RXDVS0_R_DMRXDVS_CNTCMP_OPT_B1, 0, + B1_RXDVS0_R_DMRXDVS_DQIENPRE_OPT_B1, 1, + B1_RXDVS0_R_HWRESTORE_ENA_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, valid_lat, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, rdsel_lat); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, valid_lat, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, rdsel_lat); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rxdvs2, + MISC_RXDVS2_R_DMRXDVS_DBG_MON_EN, 1, + MISC_RXDVS2_R_DMRXDVS_DBG_MON_CLR, 0, + MISC_RXDVS2_R_DMRXDVS_DBG_PAUSE_EN, 0, + MISC_RXDVS2_R_DMRXDVS_DEPTH_HALF, 1); + + for (u8 rank = RANK_0; rank < cali->support_ranks; rank++) { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rank].rk_b0_rxdvs3, + RK_B0_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B0, dq_min, + RK_B0_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B0, dq_max); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rank].rk_b0_rxdvs4, + RK_B0_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B0, dqs_min, + RK_B0_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B0, dqs_max); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rank].rk_b0_rxdvs2, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B0, scale, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B0, scale, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B0, scale, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B0, scale, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 0, + RK_B0_RXDVS2_R_RK0_DVS_FDLY_MODE_B0, 1, + RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rank].rk_b0_rxdvs1, + RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LAG, threadhold, + RK_B0_RXDVS1_R_RK0_B0_DVS_TH_LEAD, threadhold); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rank].rk_b0_rxdvs3, + RK_B1_RXDVS3_RG_RK0_ARDQ_MIN_DLY_B1, dq_min, + RK_B1_RXDVS3_RG_RK0_ARDQ_MAX_DLY_B1, dq_max); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rank].rk_b0_rxdvs4, + RK_B1_RXDVS4_RG_RK0_ARDQS0_MIN_DLY_B1, dqs_min, + RK_B1_RXDVS4_RG_RK0_ARDQS0_MAX_DLY_B1, dqs_max); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rank].rk_b0_rxdvs2, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQS_SCALE_B1, scale, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_DQ_SCALE_B1, scale, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQS_SCALE_B1, scale, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_DQ_SCALE_B1, scale, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 0, + RK_B1_RXDVS2_R_RK0_DVS_FDLY_MODE_B1, 1, + RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rank].rk_b0_rxdvs1, + RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LAG, threadhold, + RK_B1_RXDVS1_R_RK0_B1_DVS_TH_LEAD, threadhold); + } + + write32(&ch[0].phy_ao.misc_cg_ctrl1, 0xffffffff); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs1, + B0_RXDVS1_F_LEADLAG_TRACK_B0, f_leadlag); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs1, + B1_RXDVS1_F_LEADLAG_TRACK_B1, f_leadlag); + + if (rx_force_upd == 1) { + SET32_BITFIELDS(&ch[0].ao.dllfrz_ctrl, + DLLFRZ_CTRL_DLLFRZ_MON_PBREF_OPT, 1, + DLLFRZ_CTRL_DLLFRZ_BLOCKLONG, 1, + DLLFRZ_CTRL_INPUTRXTRACK_BLOCK, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs1, + B0_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs1, + B1_RXDVS1_R_DMRXDVS_UPD_CLR_NORD_B1, 1); + } + + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_rxdvs0, + B0_RXDVS0_R_RX_DLY_TRACK_ENA_B0, 1, + B0_RXDVS0_R_RX_DLY_TRACK_CG_EN_B0, 1, + B0_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B0, 1, + B0_RXDVS0_R_RX_RANKINCTL_B0, 0, + B0_RXDVS0_R_RX_RANKINSEL_B0, 1); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_rxdvs0, + B1_RXDVS0_R_RX_DLY_TRACK_ENA_B1, 1, + B1_RXDVS0_R_RX_DLY_TRACK_CG_EN_B1, 1, + B1_RXDVS0_R_RX_DLY_TRACK_SPM_CTRL_B1, 1, + B1_RXDVS0_R_RX_RANKINCTL_B1, 0, + B1_RXDVS0_R_RX_RANKINSEL_B1, 1); + + for (u8 rank = RANK_0; rank < RANK_MAX; rank++) { + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].rk[rank].rk_b0_rxdvs2, + RK_B0_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B0, 1, + RK_B0_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B0, 1, + RK_B0_RXDVS2_R_RK0_DVS_MODE_B0, 2); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].rk[rank].rk_b0_rxdvs2, + RK_B1_RXDVS2_R_RK0_RX_DLY_FAL_TRACK_GATE_ENA_B1, 1, + RK_B1_RXDVS2_R_RK0_RX_DLY_RIS_TRACK_GATE_ENA_B1, 1, + RK_B1_RXDVS2_R_RK0_DVS_MODE_B1, 2); + } + + if (rg_mode_en == 1) + SET32_BITFIELDS(&ch[0].phy_ao.misc_rg_dfs_ctrl, + MISC_RG_DFS_CTRL_RG_DPY_RXDLY_TRACK_EN, 1); + + dramc_dbg("[RX_INPUT] configuration\n"); +} + +void dig_static_setting(const struct ddr_cali *cali, dramc_subsys_config *subsys) +{ + dig_phy_config(subsys); + gating_mode_cfg(subsys); + dphy_gat_track_config(subsys); + dramc_common_config(cali, subsys); + dvfs_pre_config(subsys); + ddrphy_picg_config(); + io_release(); + rx_input_config(cali); +} + +void dig_config_shuf(const struct ddr_cali *cali, dramc_subsys_config *subsys) +{ + dig_config_shuf_alg_txca(subsys->freq_group); + dig_config_shuf_imp(subsys->freq_group); + dig_config_shuf_rxinput(); + dig_config_shuf_misc_fix(cali, subsys); + dig_config_shuf_misc_dqsgretry(subsys->freq_group); + dig_config_shuf_dbi(subsys); + dig_config_dvfs_dependence(subsys); +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index d32c268..510cb13 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -3779,6 +3779,9 @@ subsys.dfs_gp = &dvfs_config; subsys.gat_c = &gat_config; ana_init(cali, &subsys); + dig_static_setting(cali, &subsys); + dig_config_shuf(cali, &subsys); + update_initial_settings(cali); dramc_set_broadcast(DRAMC_BROADCAST_OFF); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
Patch Set 1:
(31 comments)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_dig_config.c:
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 35: dramc_dbg("Enable DLL master slave shuffle \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 47: if (subsys->a_cfg->rank_mode==0) { spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 71: if (subsys->a_cfg->new_8x_mode==1) { spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 86: ||(subsys->dvfs_core->dq_ca_open==1)) ? 0 : 1; spaces required around that '||' (ctx:ExV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 86: ||(subsys->dvfs_core->dq_ca_open==1)) ? 0 : 1; spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 232: u8 tx_ui = (freq_group <= DDRFREQ_400) ? 1: 0 ; spaces required around that ':' (ctx:VxW)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 232: u8 tx_ui = (freq_group <= DDRFREQ_400) ? 1: 0 ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 336: dramc_dbg("[RX_INPUT][Configuration] \n"); unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 362: u8 dqsien_dqsstb_mode=0; spaces required around that '=' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 372: dual_schen = (subsys->dvfs_core->dq_p2s_ratio==4) ? 0 : 1; spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 374: switch(subsys->dfs_gp->dqsien_mode) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 390: default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected subsys->dfs_gp->dqsien_mode=%1d \n", trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 390: default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected subsys->dfs_gp->dqsien_mode=%1d \n", unnecessary whitespace before a quoted newline
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 395: switch(cas_mode) { space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 405: default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected cas_mode(%d) input\n",cas_mode); space required after that ',' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 405: default: dramc_dbg("[DIG_SHUF_CONFIG] Unexpected cas_mode(%d) input\n",cas_mode); trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 411: SHU_COMMON0_FREQDIV4, subsys->dvfs_core->dq_p2s_ratio==8, spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 412: SHU_COMMON0_FDIV2, subsys->dvfs_core->dq_p2s_ratio==4, spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 414: SHU_COMMON0_DM64BITEN, !(subsys->dvfs_core->dq_p2s_ratio==4)); spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 517: default:dramc_dbg("ERROR:Unexcepted subsys->dvfs_core.dq_p2s_ratio = %d\n", trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 575: u8 hwset_mr13_op_value =0; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 576: u8 hwset_vrcg_op_value =0; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 577: u8 hwset_mr2_op_value =0; spaces required around that '=' (ctx:WxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 582: ((lp4_init->work_fsp & 1) << 6) | (( 0 << 5) | 8); space prohibited after that open parenthesis '('
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 843: dramc_dbg("Enter into dvfs_pre_config\n"); Prefer using '"%s...", __func__' to using 'dvfs_pre_config', this function's name, in a string
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 909: MISC_DVFSCTL_R_DVFS_PICG_MARGIN_NEW, (ref_104m_en==1)?3:1, spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 910: MISC_DVFSCTL_R_DVFS_PICG_MARGIN2_NEW, (ref_104m_en==1)?3:1, spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 911: MISC_DVFSCTL_R_DVFS_PICG_MARGIN3_NEW, (ref_104m_en==1)?3:1); spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 925: (ref_104m_en==1) ? 6 : 4); spaces required around that '==' (ctx:VxV)
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 964: MISC_CG_CTRL0_RG_CG_PHY_OFF_DIABLE, !misc_cg_en, 'DIABLE' may be misspelled - perhaps 'DISABLE'?
https://review.coreboot.org/c/coreboot/+/44728/1/src/soc/mediatek/mt8192/dra... PS1, Line 1105: dramc_dbg("[RX_INPUT] configuration \n"); unnecessary whitespace before a quoted newline
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, Duan huayang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44728
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,249 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/2
huayang duan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
Patch Set 2:
for test whether xixi can received the review commit from email notify.
Yidi Lin has uploaded a new patch set (#24) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,249 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/24
Yidi Lin has uploaded a new patch set (#34) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,249 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/34
Yidi Lin has uploaded a new patch set (#36) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,249 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/36
Yidi Lin has uploaded a new patch set (#41) to the change originally created by CK HU. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
soc/mediatek/mt8192: Do dramc digital init setting
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: If84def990983fae32506c1cd409bd1a1e3a550cd --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_dig_config.c M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 3 files changed, 1,249 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44728/41
CK HU has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44728 )
Change subject: soc/mediatek/mt8192: Do dramc digital init setting ......................................................................
Abandoned
Useless
-
build bot (Jenkins) (Code Review) -
CK HU (Code Review)
-
huayang duan (Code Review)
-
Yidi Lin (Code Review)