[S] Change in coreboot[master]: nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
Attention is currently required from: Angel Pons, Alexander Couzens.
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69289 )
Change subject: nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree ......................................................................
nb/intel/haswell: Hook up PCI domain and CPU cluster ops to devicetree
Change-Id: I955274bc6bda587201f130762c0735c36f5501d1 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/hp/folio_9480m/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb M src/mainboard/lenovo/haswell/variants/w541/devicetree.cb M src/mainboard/msi/h81m-p33/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/northbridge/intel/haswell/northbridge.c 11 files changed, 32 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/69289/1
diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index 43a65f8..f24dbf1 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -4,6 +4,7 @@ register "gpu_ddi_e_connected" = "1"
device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end @@ -11,6 +12,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x1849 0x0c00 inherit
device pci 00.0 on end # Host bridge diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 7b08af9..ccdcaa4 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -4,6 +4,7 @@ register "gpu_ddi_e_connected" = "1"
device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end @@ -11,6 +12,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops device pci 00.0 on # Host bridge subsystemid 0x1849 0x0c00 end diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 8eada25..bb57c44 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -14,6 +14,7 @@ register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip @@ -22,6 +23,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x1ae0 0xc000 inherit device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index d989545..d09d7a1 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -16,6 +16,7 @@ register "usb_xhci_on_resume" = "true"
device cpu_cluster 0 on + ops haswell_cpu_bus_ops chip cpu/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip @@ -24,6 +25,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb index fca4f16..fad17f0 100644 --- a/src/mainboard/hp/folio_9480m/devicetree.cb +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -14,12 +14,14 @@ }" register "usb_xhci_on_resume" = "true" device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x103c 0x22da inherit device pci 00.0 on end # Host bridge device pci 02.0 on end # Internal graphics VGA controller diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 37cff88..fb4e466 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -12,6 +12,7 @@ register "gpu_dp_b_hotplug" = "0x06"
device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end # Magic APIC ID to locate this chip @@ -20,6 +21,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller
diff --git a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb index c8772cc..9f5c8ac 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/t440p/devicetree.cb @@ -14,12 +14,14 @@ }" register "ec_present" = "true" device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x17aa 0x220e inherit
device pci 00.0 on end # Host bridge diff --git a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb index ae720e8..5dc9f1a 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb +++ b/src/mainboard/lenovo/haswell/variants/w541/devicetree.cb @@ -14,12 +14,14 @@ }" register "ec_present" = "true" device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x17aa 0x2211 inherit
device pci 00.0 on end # Host bridge diff --git a/src/mainboard/msi/h81m-p33/devicetree.cb b/src/mainboard/msi/h81m-p33/devicetree.cb index e079770..081b1ecd 100644 --- a/src/mainboard/msi/h81m-p33/devicetree.cb +++ b/src/mainboard/msi/h81m-p33/devicetree.cb @@ -3,12 +3,14 @@ chip northbridge/intel/haswell register "gpu_ddi_e_connected" = "1" device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end end end device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x1462 0x7817 inherit device pci 00.0 on end # Host bridge device pci 01.0 on end # PEG diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 6cd3ab7..2d1e8189 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/haswell
device cpu_cluster 0 on + ops haswell_cpy_bus_ops chip cpu/intel/haswell device lapic 0 on end device lapic 0xacac off end @@ -10,6 +11,7 @@ end
device domain 0 on + ops haswell_pci_domain_ops subsystemid 0x15d9 0x0803 inherit
device pci 00.0 on end # Host bridge diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index e84ba76..e11eb1c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -34,7 +34,7 @@ return NULL; }
-static struct device_operations pci_domain_ops = { +struct device_operations haswell_pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, @@ -557,23 +557,12 @@ .devices = mc_pci_device_ids, };
-static struct device_operations cpu_bus_ops = { +struct device_operations haswell_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = mp_cpu_bus_init, };
-static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type. */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - struct chip_operations northbridge_intel_haswell_ops = { CHIP_NAME("Intel Haswell integrated Northbridge") - .enable_dev = enable_dev, };
-
Arthur Heymans (Code Review)