Change in coreboot[master]: mb/google/drallion: change servo board debug to UART 0

[EricR Lai (Code Review)]

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35132 )

Change subject: mb/google/drallion: change servo board debug to UART 0
......................................................................

mb/google/drallion: change servo board debug to UART 0

Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.

BUG=b:139095062
BRANCH=N/A
TEST=Build without error

Signed-off-by: Eric Lai 
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/drallion/variants/drallion/gpio.c
2 files changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35132/1

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 575b610..54184f0 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -355,7 +355,7 @@
    		end
    	end # I2C #4
    	device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
+		device pci 19.2 off end # UART #2
    	device pci 1a.0 off end # eMMC
    	device pci 1c.0 off end # PCI Express Port 1 (USB)
    	device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -374,7 +374,7 @@
    	device pci 1d.4 on
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
    	end # PCI Express Port 13 (x4)
-		device pci 1e.0 off end # UART #0
+		device pci 1e.0 on  end # UART #0
    	device pci 1e.1 off end # UART #1
    	device pci 1e.2 off end # GSPI #0
    	device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index ff0240c..ebe5ee2 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -87,8 +87,8 @@
 /* SML0ALERT# */	PAD_NC(GPP_C5, DN_20K),
 /* SM1CLK */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
 /* SM1DATA */		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
-/* UART0_RXD */		PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
-/* UART0_TXD */		PAD_NC(GPP_C9, NONE),
+/* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */
+/* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */
 /* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
 /* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
 /* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
@@ -100,8 +100,8 @@
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
 /* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
-/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
-/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
+/* UART2_RXD */		PAD_NC(GPP_C20, NONE),
+/* UART2_TXD */		PAD_NC(GPP_C21, NONE),
 /* UART2_RTS# */	PAD_NC(GPP_C22, NONE),
 /* UART2_CTS# */	PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
    			 LEVEL, NONE), /* TS_INT# */

[Mathew King (Code Review)]

Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35132 )

Change subject: mb/google/drallion: change servo board debug to UART 0
......................................................................

Patch Set 1: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35132 )

Change subject: mb/google/drallion: change servo board debug to UART 0
......................................................................

mb/google/drallion: change servo board debug to UART 0

Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.

BUG=b:139095062
BRANCH=N/A
TEST=Build without error

Signed-off-by: Eric Lai 
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) 
Reviewed-by: Mathew King 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/drallion/variants/drallion/gpio.c
2 files changed, 6 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Mathew King: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 575b610..54184f0 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -355,7 +355,7 @@
    		end
    	end # I2C #4
    	device pci 19.1 off end # I2C #5
-		device pci 19.2 on  end # UART #2
+		device pci 19.2 off end # UART #2
    	device pci 1a.0 off end # eMMC
    	device pci 1c.0 off end # PCI Express Port 1 (USB)
    	device pci 1c.1 off end # PCI Express Port 2 (USB)
@@ -374,7 +374,7 @@
    	device pci 1d.4 on
    		smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
    	end # PCI Express Port 13 (x4)
-		device pci 1e.0 off end # UART #0
+		device pci 1e.0 on  end # UART #0
    	device pci 1e.1 off end # UART #1
    	device pci 1e.2 off end # GSPI #0
    	device pci 1e.3 off end # GSPI #1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c
index ff0240c..ebe5ee2 100644
--- a/src/mainboard/google/drallion/variants/drallion/gpio.c
+++ b/src/mainboard/google/drallion/variants/drallion/gpio.c
@@ -87,8 +87,8 @@
 /* SML0ALERT# */	PAD_NC(GPP_C5, DN_20K),
 /* SM1CLK */		PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
 /* SM1DATA */		PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
-/* UART0_RXD */		PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
-/* UART0_TXD */		PAD_NC(GPP_C9, NONE),
+/* UART0_RXD */		PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */
+/* UART0_TXD */		PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */
 /* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
 /* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
 /* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
@@ -100,8 +100,8 @@
 /* I2C0_SCL */		PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
 /* I2C1_SDA */		PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
 /* I2C1_SCL */		PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
-/* UART2_RXD */		PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
-/* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
+/* UART2_RXD */		PAD_NC(GPP_C20, NONE),
+/* UART2_TXD */		PAD_NC(GPP_C21, NONE),
 /* UART2_RTS# */	PAD_NC(GPP_C22, NONE),
 /* UART2_CTS# */	PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
    			 LEVEL, NONE), /* TS_INT# */