Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73311 )
Change subject: include/device/pci_def.h: Fix typo in comment ......................................................................
include/device/pci_def.h: Fix typo in comment
Fix typo in the comment for Common Clock Configuration.
Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16 Signed-off-by: Werner Zeh werner.zeh@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Elyes Haouas ehaouas@noos.fr Reviewed-by: Frans Hendriks fhendriks@eltan.com --- M src/include/device/pci_def.h 1 file changed, 17 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Frans Hendriks: Looks good to me, approved
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index c13e054..69ff79d 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -431,7 +431,7 @@ #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ -#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock Configuration */ #define PCI_EXP_EN_CLK_PM 0x100 /* Enable Clock Power Management */ #define PCI_EXP_LNKSTA 18 /* Link Status */ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */