Change in coreboot[master]: soc/amd/cezanne/romstage: Store early dram region

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50338 )

Change subject: soc/amd/cezanne/romstage: Store early dram region
......................................................................

soc/amd/cezanne/romstage: Store early dram region

Needed so we can reserve the memory.

Signed-off-by: Raul E Rangel 
Change-Id: I8f5bb9d97932f75ca4ce22fbe9df4c0148acbea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50338
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Held 
Reviewed-by: Angel Pons 
---
M src/soc/amd/cezanne/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index c7e7e5c..773c6a9 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
+#include <amdblocks/memmap.h>
 #include <arch/cpu.h>
 #include <console/console.h>
 #include <console/uart.h>
@@ -33,5 +34,7 @@

fsp_memory_init(acpi_is_wakeup_s3());

+	memmap_stash_early_dram_usage();
+
    run_ramstage();
 }