Change in coreboot[master]: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init

[Maulik V Vaghela (Code Review)]

Hello Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Krishna P Bhat D, Aamir Bohra, Ronak Kanabar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42462

to look at the new patch set (#3).

Change subject: soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init
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soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart Init

Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot

BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting

Cq-Depend:42471

Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela 
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M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/42462/3