Change in ...coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969

Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
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soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point

This moves some boilerplate like setting up timestamps and entering
postcar to a common location.

Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/baytrail/romstage/Makefile.inc
M src/soc/intel/baytrail/romstage/romstage.c
2 files changed, 4 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1

diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index f1a3463..8f009bd 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,5 +1,6 @@
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 cpu_incs-y += $(obj)/fmap_config.h
+romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += raminit.c
 romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index cc3bcd9..2a530b4 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -21,6 +21,7 @@
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <cbmem.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #if CONFIG(EC_GOOGLE_CHROMEEC)
 #include <ec/google/chromeec/ec.h>
@@ -49,8 +50,6 @@
  * Because we can't use global variables the stack is used for allocations --
  * thus the need to call back and forth. */

-static void platform_enter_postcar(void);
-
 static void program_base_addresses(void)
 {
    uint32_t reg;
@@ -166,18 +165,12 @@
 }

/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc, uint32_t bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
    struct mrc_params mrc_params;
    struct chipset_power_state *ps;
    int prev_sleep_state;

-	/* Save initial timestamp from bootblock. */
-	timestamp_init(tsc);
-
-	/* Save romstage begin */
-	timestamp_add_now(TS_START_ROMSTAGE);
-
    program_base_addresses();

tco_disable();
@@ -215,25 +208,13 @@
    timestamp_add_now(TS_AFTER_INITRAM);

romstage_handoff_init(prev_sleep_state == ACPI_S3);
-
-	platform_enter_postcar();
-
-	/* We don't return here */
-}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
-	romstage_main(base_timestamp, bist);
 }

#define ROMSTAGE_RAM_STACK_SIZE 0x5000

/* setup_stack_and_mtrrs() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use. */
-static void platform_enter_postcar(void)
+void platform_enter_postcar(void)
 {
    struct postcar_frame pcf;
    uintptr_t top_of_ram;

Change in coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point

[Arthur Heymans (Code Review)]

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32969 )

Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
......................................................................

Abandoned