Patch set updated for coreboot: 659adfd jetway/nf81-t56n-lf: Move pc80 driver from rom to ram stage

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5509

-gerrit

commit 659adfddefa68695a2a0e75628de64b3b7f70ded
Author: Edward O'Callaghan 
Date:   Tue Apr 15 20:45:13 2014 +1000

jetway/nf81-t56n-lf: Move pc80 driver from rom to ram stage

Avoid #including .c files from pc80 driver by migrating i825{4,9} init's
    from romstage to ramstage.

Change-Id: I4cd87317fb44cd2bda09f3df1c0635cdc87943e2
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 11 +++++++++++
 src/mainboard/jetway/nf81-t56n-lf/romstage.c  | 12 ------------
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b3c9e3d..7904a01 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -31,6 +31,9 @@
 #include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include <southbridge/amd/sb800/sb800.h>

+#include <pc80/i8254.h>
+#include <pc80/i8259.h>
+
 void set_pcie_reset(void);
 void set_pcie_dereset(void);

@@ -58,6 +61,14 @@ static void mainboard_enable(device_t dev)
 {
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

+	/* Initialize i8259 pic */
+	post_code(0x43);
+	setup_i8259 ();
+
+	/* Initialize i8254 timers */
+	post_code(0x44);
+	setup_i8254 ();
+
 /*
  * The mainboard is the first place that we get control in ramstage. Check
  * for S3 resume and call the approriate AGESA/CIMx resume functions.
diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
index 848faf7..c6ed7b8 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c
@@ -44,10 +44,6 @@
 #include <superio/fintek/common/fintek.h>
 #include <superio/fintek/f71869ad/f71869ad.h>

-/* FIXME: should not include .c files */
-#include "drivers/pc80/i8254.c"
-#include "drivers/pc80/i8259.c"
-
 /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
 #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)

@@ -174,14 +170,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    }
 #endif /* CONFIG_HAVE_ACPI_RESUME */

-	/* Initialize i8259 pic */
-	post_code(0x43);
-	setup_i8259 ();
-
-	/* Initialize i8254 timers */
-	post_code(0x44);
-	setup_i8254 ();
-
    post_code(0x50);
    copy_and_run();
    printk(BIOS_ERR, "Error: copy_and_run() returned!\n");