New subject: Change in coreboot[master]: vc/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE build warnings/errors

16 Nov 2019

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36880 )
Change subject: vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warnings/errors
......................................................................
vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warnings/errors
Fix the format-related warnings/errors which happen with IDS_HDT_CONSOLE enabled
(IDSOPT_IDS_ENABLED TRUE and IDSOPT_TRACING_ENABLED TRUE at board/OptionsIds.h).
Joined errors log before a fix is available at https://pastebin.com/RZQBvTEc and
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/XRDT...
Signed-off-by: Mike Banon mikebdp2@gmail.com
Change-Id: I4c4f8f575b2f72451e7c60ba708d1f389d102e44
---
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
M src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
M src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
M src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
M src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
M src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
M src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c
M src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
19 files changed, 38 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/36880/1

diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
index 714f970..ef18c82 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16MmioMap.c
@@ -155,7 +155,7 @@
       UnusedMmioPair++;
     }
     IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
-    IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+    IDS_HDT_CONSOLE (MAIN_FLOW, "%08llx%08llx    %08llx%08llx", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
                                                          MmioRange[MmioPair].Base & 0xFFFFFFFF,
                                                         (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
                                                          MmioRange[MmioPair].Limit & 0xFFFFFFFF);
@@ -172,7 +172,7 @@
   NewMmioRange.Base = AmdAddMmioParams.BaseAddress;
   NewMmioRange.Limit = AmdAddMmioParams.BaseAddress + AmdAddMmioParams.Length;
   NewMmioRange.Attribute = AmdAddMmioParams.Attributes;
-  IDS_HDT_CONSOLE (MAIN_FLOW, "req %08x%08x    %08x%08x\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF,
+  IDS_HDT_CONSOLE (MAIN_FLOW, "req %08llx%08llx    %08llx%08llx\n", (NewMmioRange.Base >> 32) & 0xFFFFFFFF,
                                                          NewMmioRange.Base & 0xFFFFFFFF,
                                                         (NewMmioRange.Limit >> 32) & 0xFFFFFFFF,
                                                          NewMmioRange.Limit & 0xFFFFFFFF);
@@ -414,7 +414,7 @@
           PciAddress.Address.Function = FUNC_1;
           for (MmioPair = 0; MmioPair < MMIO_REG_PAIR_NUM; MmioPair++) {
             IDS_HDT_CONSOLE (MAIN_FLOW, " %02d ", MmioPair);
-            IDS_HDT_CONSOLE (MAIN_FLOW, "%08x%08x    %08x%08x", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
+            IDS_HDT_CONSOLE (MAIN_FLOW, "%08llx%08llx    %08llx%08llx", (MmioRange[MmioPair].Base >> 32) & 0xFFFFFFFF,
                                                                  MmioRange[MmioPair].Base & 0xFFFFFFFF,
                                                                 (MmioRange[MmioPair].Limit >> 32) & 0xFFFFFFFF,
                                                                  MmioRange[MmioPair].Limit & 0xFFFFFFFF);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
index b3db886..3757ab9 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
@@ -148,7 +148,7 @@
           }
         }
       } else {
-        IDS_HDT_CONSOLE (CPU_TRACE, "  Force Ucode loaded from offset %x\n", ForceLoadMicrocodePatchPtr);
+        IDS_HDT_CONSOLE (CPU_TRACE, "  Force Ucode loaded from offset %x\n", (UINT32)ForceLoadMicrocodePatchPtr);
         if (LoadMicrocode (ForceLoadMicrocodePatchPtr, StdHeader)) {
           Status = TRUE;
         } else {
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
index 30e194e..c09ff55 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/AmdInitReset.c
@@ -154,7 +154,7 @@
IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitReset: Start\n\n");
-  IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", &UserOptions.VersionString);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "\n*** %s ***\n\n", (CHAR8 *)&UserOptions.VersionString);
AGESA_TESTPOINT (TpIfAmdInitResetEntry, &ResetParams->StdHeader);
   ASSERT (ResetParams != NULL);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
index 9da575c..7ee6dc5 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3RestoreState.c
@@ -165,7 +165,7 @@
   PCI_ADDR              PciAddress;
   UINTN                 Index;
   S3SaveTableRecordPtr = (UINT8 *) S3SaveTablePtr + sizeof (S3_SAVE_TABLE_HEADER);
-  IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore\n", ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
+  IDS_HDT_CONSOLE (S3_TRACE, "Start S3 restore - Address: 0x%08x\n", (UINT16) ((S3_WRITE_OP_HEADER *) S3SaveTableRecordPtr)->Address);
   while ((UINT8 *) S3SaveTableRecordPtr < ((UINT8 *) S3SaveTablePtr + S3SaveTablePtr->SaveOffset)) {
     switch  (*(UINT16 *) S3SaveTableRecordPtr) {
     case  SAVE_STATE_IO_WRITE_OPCODE:
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
index c81c877..68976ee 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Common/S3SaveState.c
@@ -268,7 +268,7 @@
     }
   }
   S3_SCRIPT_DEBUG_CODE (
-    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
     S3SaveDebugPrintHexArray (StdHeader, Buffer, Count, Width);
     IDS_HDT_CONSOLE (S3_TRACE, "\n");
     );
@@ -333,7 +333,7 @@
     }
   }
   S3_SCRIPT_DEBUG_CODE (
-    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
     S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
     IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
     S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@@ -409,7 +409,7 @@
     }
   }
   S3_SCRIPT_DEBUG_CODE (
-    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08x Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: %s Address: 0x%08llx Data: ", S3SaveDebugOpcodeString (StdHeader, OpCode), Address);
     S3SaveDebugPrintHexArray (StdHeader, Data, 1, Width);
     IDS_HDT_CONSOLE (S3_TRACE, " Mask: ");
     S3SaveDebugPrintHexArray (StdHeader, DataMask, 1, Width);
@@ -481,7 +481,7 @@
   SaveOffsetPtr->OpCode = OpCode;
   SaveOffsetPtr->Length = InformationLength;
   S3_SCRIPT_DEBUG_CODE (
-    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: Info: %s \n", Information);
+    IDS_HDT_CONSOLE (S3_TRACE, "  S3 Save: Info: %s \n", (CHAR8 *)Information);
     );
   LibAmdMemCopy (
     (UINT8 *) SaveOffsetPtr + sizeof (S3_INFO_OP_HEADER),
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
index 4bea9fb..60cb936 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitEnvDef.c
@@ -138,7 +138,7 @@
FchParams = (FCH_DATA_BLOCK *) AllocHeapParams.BufferPtr;
   ASSERT (FchParams != NULL);
-  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
+  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, (UINT32)FchParams);
// Load private data block with default
   *FchParams = InitEnvCfgDefault;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
index 9cbffd7..606c3fc 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/InitResetDef.c
@@ -71,7 +71,7 @@
FchParams = (FCH_RESET_DATA_BLOCK *) AllocHeapParams.BufferPtr;
   ASSERT (FchParams != NULL);
-  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, FchParams);
+  IDS_HDT_CONSOLE (FCH_TRACE, "    FCH Reset Data Block Allocation: [0x%x], Ptr = 0x%08x\n", AgesaStatus, (UINT32)FchParams);
*FchParams = InitResetCfgDefault;
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
index 34990c5..02d65ed 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbCommonLib/GnbLib.c
@@ -482,7 +482,7 @@
       Index += 4;
       break;
     case 4:
-      IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4));
+      IDS_HDT_CONSOLE (GNB_TRACE, "%08x%08x", *(UINT32 *) ((UINT8 *) Buffer + Index), *(UINT32 *) ((UINT8 *) Buffer + Index + 4));
       Index += 8;
       break;
     default:
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
index ae0128a..1e8b679 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c
@@ -255,7 +255,7 @@
     );
   IDS_HDT_CONSOLE (GFX_MISC, "  UmaMode - %s\n", (Gfx->UmaInfo.UmaMode == UMA_NONE) ? "No UMA" : "UMA");
   if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
-    IDS_HDT_CONSOLE (GFX_MISC, "  UmaBase - 0x%x\n", Gfx->UmaInfo.UmaBase);
+    IDS_HDT_CONSOLE (GFX_MISC, "  UmaBase - 0x%llx\n", Gfx->UmaInfo.UmaBase);
     IDS_HDT_CONSOLE (GFX_MISC, "  UmaSize - 0x%x\n", Gfx->UmaInfo.UmaSize);
     IDS_HDT_CONSOLE (GFX_MISC, "  UmaAttributes - 0x%x\n", Gfx->UmaInfo.UmaAttributes);
   }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
index 7b5f3ef..532b164 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c
@@ -495,7 +495,7 @@
   PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3Ptr->ulPowerplayTable;
   ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) (PpTable) + PpTable->usExtendendedHeaderOffset);
   IDS_HDT_CONSOLE (GFX_MISC, "    ExtendedHeader  usSize %d\n", ExtendedHeader->usSize);
-  IDS_HDT_CONSOLE (GFX_MISC, "                    SizeOf %d\n", sizeof(ATOM_PPLIB_EXTENDEDHEADER));
+  IDS_HDT_CONSOLE (GFX_MISC, "                    SizeOf %ld\n", sizeof(ATOM_PPLIB_EXTENDEDHEADER));
IDS_HDT_CONSOLE (GFX_MISC, "    ucHtcTmpLmt  0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ucHtcTmpLmt);
   IDS_HDT_CONSOLE (GFX_MISC, "    ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 0x%X\n", SystemInfoTableV3Ptr->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
index 4e83c44..656f737 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c
@@ -1158,7 +1158,7 @@
   ClockInfoArrayPtr = (CLOCK_INFO_ARRAY *) ((UINT8 *) PpTable + PpTable->usClockInfoArrayOffset);
   IDS_HDT_CONSOLE (GFX_MISC, "  < --- SW State Table ---------> \n");
   for (Index = 0; Index < StateArray->ucNumEntries; Index++) {
-    IDS_HDT_CONSOLE (GFX_MISC, "  State #%d\n", Index + 1
+    IDS_HDT_CONSOLE (GFX_MISC, "  State #%ld\n", Index + 1
       );
     IDS_HDT_CONSOLE (GFX_MISC, "    Classification 0x%x\n",
        NonClockInfoArrayPtr->NonClockInfo[StatesPtr->nonClockInfoIndex].usClassification
@@ -1173,7 +1173,7 @@
     ExtendedHeader = (ATOM_PPLIB_EXTENDEDHEADER *) ((UINT8 *) PpTable +
       PpTable->usExtendendedHeaderOffset);
-    IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader = %08x\n", ExtendedHeader);
+    IDS_HDT_CONSOLE (GNB_TRACE, "ExtendedHeader = %08x\n", (UINT32)ExtendedHeader);
VceClockInfoArray = (VCECLOCKINFOARRAY *) ((UINT8 *) PpTable +
         ExtendedHeader->usVCETableOffset + sizeof (ATOM_PPLIB_VCE_TABLE));
@@ -1203,7 +1203,7 @@
     IDS_HDT_CONSOLE (GFX_MISC, "  < --- VCE Voltage Record Table ---> \n");
     for (Index = 0; Index < VceClockVoltageLimitTable->numEntries; Index++) {
       EclkIndex = VceClockVoltageLimitTable->entries[Index].ucVCEClockInfoIndex;
-      IDS_HDT_CONSOLE (GFX_MISC, "  VCE Voltage Record #%d\n", Index
+      IDS_HDT_CONSOLE (GFX_MISC, "  VCE Voltage Record #%ld\n", Index
         );
       IDS_HDT_CONSOLE (GFX_MISC, "    ECLK = %d\n",
         VceClockInfoArray->entries[EclkIndex].usECClkLow | (VceClockInfoArray->entries[EclkIndex].ucECClkHigh << 16)
@@ -1216,7 +1216,7 @@
IDS_HDT_CONSOLE (GFX_MISC, "  < --- SAMU Voltage Record Table ---> \n");
     for (Index = 0; Index < SamuClockVoltLimitTable->numEntries; Index++) {
-      IDS_HDT_CONSOLE (GFX_MISC, "  SAMU Voltage Record #%d\n", Index
+      IDS_HDT_CONSOLE (GFX_MISC, "  SAMU Voltage Record #%ld\n", Index
         );
       IDS_HDT_CONSOLE (GFX_MISC, "    SAMCLK = %d\n",
           SamuClockVoltLimitTable->entries[Index].usSAMClockLow |
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
index b26679b..d8b351c 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c
@@ -371,7 +371,7 @@
     BaseAddress |= Value;
if ((BaseAddress & 0xfffffffffffffffe) != 0x0) {
-      IDS_HDT_CONSOLE (GNB_TRACE, "  Enable IOMMU MMIO at address %x for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
+      IDS_HDT_CONSOLE (GNB_TRACE, "  Enable IOMMU MMIO at address %llx for Socket %d Silicon %d\n", BaseAddress, GnbGetSocketId (GnbHandle) , GnbGetSiliconId (GnbHandle));
       GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x8), AccessS3SaveWidth32, 0xFFFFFFFF, 0x0, StdHeader);
       GnbLibPciRMW (GnbIommuPciAddress.AddressValue | (CapabilityOffset + 0x4), AccessS3SaveWidth32, 0xFFFFFFFE, 0x1, StdHeader);
     } else {
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
index 27e7bce..c7993fd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c
@@ -557,7 +557,11 @@
       EngineList->Type.Port.Address.Address.Device,
       EngineList->Type.Port.Address.Address.Function
       );
-    IDS_HDT_CONSOLE (PCIE_MISC, "          Misc Control  - 0x%02x\n", EngineList->Type.Port.PortData.MiscControls);
+    IDS_HDT_CONSOLE (PCIE_MISC, "          MiscControls[LinkComplianceMode/LinkSafeMode/SbLink/ClkPmSupport]  - 0x%02x/0x%02x/0x%02x/0x%02x\n\n",
+      EngineList->Type.Port.PortData.MiscControls.LinkComplianceMode,
+      EngineList->Type.Port.PortData.MiscControls.LinkSafeMode,
+      EngineList->Type.Port.PortData.MiscControls.SbLink,
+      EngineList->Type.Port.PortData.MiscControls.ClkPmSupport);
     IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Dev Number  - %d\n", EngineList->Type.Port.NativeDevNumber);
     IDS_HDT_CONSOLE (PCIE_MISC, "          Native PCI Func Number - %d\n", EngineList->Type.Port.NativeFunNumber);
     IDS_HDT_CONSOLE (PCIE_MISC, "          Hotplug - %s\n",
@@ -736,7 +740,7 @@
     EngineDescriptor->EngineData.EndLane
   );
   if (EngineDescriptor->EngineData.EngineType == PciePortEngine) {
-    IDS_HDT_CONSOLE (PCIE_MISC, "    PortPresent - %d\n    ChannelType  - %d\n    DeviceNumber - %d\n    FunctionNumber - %d\n    LinkSpeedCapability - %d\n    LinkAspm - %d\n    LinkHotplug - %d\n    ResetId - %d\n    SB link - %d\n    MiscControls - 0x%02x\n" ,
+    IDS_HDT_CONSOLE (PCIE_MISC, "    PortPresent - %d\n    ChannelType  - %d\n    DeviceNumber - %d\n    FunctionNumber - %d\n    LinkSpeedCapability - %d\n    LinkAspm - %d\n    LinkHotplug - %d\n    ResetId - %d\n    MiscControls[LinkComplianceMode/LinkSafeMode/SbLink/ClkPmSupport] - 0x%02x/0x%02x/0x%02x/0x%02x\n" ,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.PortPresent,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ChannelType,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.DeviceNumber,
@@ -745,8 +749,10 @@
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkAspm,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.LinkHotplug,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.ResetId,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkComplianceMode,
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.LinkSafeMode,
       ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.SbLink,
-      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls
+      ((PCIe_PORT_DESCRIPTOR *) EngineDescriptor)->Port.MiscControls.ClkPmSupport
     );
   }
   if (EngineDescriptor->EngineData.EngineType == PcieDdiEngine) {
@@ -784,7 +790,7 @@
   for (ComplexIndex = 0; ComplexIndex < NumberOfComplexes; ++ComplexIndex) {
     CurrentComplexDescriptor = PcieInputParserGetComplexDescriptor (ComplexDescriptor, ComplexIndex);
     NumberOfEngines = PcieInputParserGetNumberOfEngines (CurrentComplexDescriptor);
-    IDS_HDT_CONSOLE (PCIE_MISC, "  ComplexDescriptor SocketId - %d\n  NumberOfEngines - %d\n",
+    IDS_HDT_CONSOLE (PCIE_MISC, "  ComplexDescriptor SocketId - %d\n  NumberOfEngines - %ld\n",
         ComplexDescriptor->SocketId,
         NumberOfEngines
       );
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c
index 9113029..2c3f232 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c
@@ -104,19 +104,19 @@
     //Verify the SCS block signature
     ASSERT (*(UINT32 *)ScsDataPtr == GnbSmuInitLibV7136_macro0);
     if (*(UINT32 *)ScsDataPtr != GnbSmuInitLibV7136_macro0) {
-      IDS_HDT_CONSOLE (GNB_TRACE, "Verify SCS Binary fail\n", ScsDataPtr);
+      IDS_HDT_CONSOLE (GNB_TRACE, "Verify SCS Binary fail - ScsDataPtr: 0x%08x\n", (UINT32)ScsDataPtr);
       return AGESA_ERROR;
     }
//Load SCS block
-    IDS_HDT_CONSOLE (GNB_TRACE, "Load SCS @%08x\n", ScsDataPtr);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Load SCS @%08x\n", (UINT32)ScsDataPtr);
     DevObject.DevPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0);
     DevObject.GnbHandle = GnbHandle;
     DevObject.StdHeader = StdHeader;
     GnbSmuServiceRequestV7 (&DevObject, 0x50, (UINT32) (UINTN) ScsDataPtr, 0);
//Get SCS result and save to Heap
-    IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result\n", ScsDataPtr);
+    IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result - ScsDataPtr: 0x%08x\n", (UINT32)ScsDataPtr);
     Status = GnbSmuInitLibV7139_fun1 (GnbHandle, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "Get SCS Result %s\n", (Status == AGESA_SUCCESS) ? "Success" : "Fail");
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
index d75bf3e..17ef27e 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/IDS/Debug/IdsDebug.c
@@ -129,7 +129,7 @@
file = (FileCode >> 16);
   line = (FileCode & 0xFFFF);
-  IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%x] Line[%x]\n", (UINTN) file, (UINTN) line);
+  IDS_HDT_CONSOLE (MAIN_FLOW, "ASSERT on File[%lx] Line[%lx]\n", (UINTN) file, (UINTN) line);
   IDS_HDT_CONSOLE_FLUSH_BUFFER (NULL);
   IDS_HDT_CONSOLE_ASSERT (FileCode);
 //  IdsErrorStop (FileCode);
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
index b355d6b..ef40521 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c
@@ -221,7 +221,7 @@
     //
     Va.AdjustValue = Vref = (Vref - 15) << 1;
     Status = AgesaExternalVoltageAdjust ((UINTN)CallOutIdInfo.IdInformation, &Va);
-    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm Vref = %c%d%    ", (Va.AdjustValue < 0) ? '-':'+', (Va.AdjustValue < 0) ? (0 - Va.AdjustValue) : Va.AdjustValue );
+    IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tDimm Vref = %c%d    ", (Va.AdjustValue < 0) ? '-':'+', (Va.AdjustValue < 0) ? (0 - Va.AdjustValue) : Va.AdjustValue );
     if (Status != AGESA_SUCCESS) {
       IDS_HDT_CONSOLE (MEM_FLOW, "* Dimm Vref Callout Failed *");
     }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
index 6a9e873..5aab7c4 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c
@@ -1242,7 +1242,7 @@
   IDS_HDT_CONSOLE_DEBUG_CODE (
     IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Positive Vref Offset from V-Nom for ChipSel %02x = + %02x\n", NBPtr->TechPtr->ChipSel, Data->SmallestPosMaxVrefperCS[NBPtr->TechPtr->ChipSel]);
     if (Data->SmallestPosMaxVrefperCS[NBPtr->TechPtr->ChipSel] == 0) {
-      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n");
+      IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n", NBPtr->TechPtr->ChipSel);
     } else {
       IDS_HDT_CONSOLE (MEM_FLOW, "\t\t\tSmallest Max Negative Vref Offset from V-Nom for ChipSel %02x = - %02x\n", NBPtr->TechPtr->ChipSel, Data->SmallestNegMaxVrefperCS[NBPtr->TechPtr->ChipSel]);
     }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
index d497aec..13e5d18 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c
@@ -389,7 +389,7 @@
           AGESA_TESTPOINT (TpProcMemAfterAgesaReadSpd, &MemPtr->StdHeader);
           if (AgesaStatus == AGESA_SUCCESS) {
             DimmSPDPtr->DimmPresent = TRUE;
-            IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer);
+            IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, (UINT32)SpdParam.Buffer);
           } else {
             DimmSPDPtr->DimmPresent = FALSE;
           }
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
index 9bb9440..5ee5311 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c
@@ -1072,7 +1072,7 @@
   IDS_HDT_CONSOLE_DEBUG_CODE (
     IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Positive Vref Offset from V-Nom for ChipSel %02x = + %02x\n", TechPtr->ChipSel, Data->SmallestPosMaxVrefperCS[TechPtr->ChipSel]);
     if (Data->SmallestPosMaxVrefperCS[TechPtr->ChipSel] == 0) {
-      IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n");
+      IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = 00\n", TechPtr->ChipSel);
     } else {
       IDS_HDT_CONSOLE (MEM_FLOW, "Smallest Max Negative Vref Offset from V-Nom for ChipSel %02x = - %02x\n", TechPtr->ChipSel, Data->SmallestNegMaxVrefperCS[TechPtr->ChipSel]);
     }
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4c4f8f575b2f72451e7c60ba708d1f389d102e44
Gerrit-Change-Number: 36880
Gerrit-PatchSet: 1
Gerrit-Owner: Mike Banon mikebdp2@gmail.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: vendorcode/amd/agesa/f16kb: fix the IDS_HDT_CONSOLE compilation warni...