Change in coreboot[master]: drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs

[Subrata Banik (Code Review)]

Attention is currently required from: Arthur Heymans, Raul Rangel, Mariusz Szafrański, Jonathan Zhang, Andrey Petrov, Patrick Rudolph, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Suresh Bellampalli, Christian Walter, Tim Wawrzynczak, Vanessa Eusebio, Nick Vaccaro, Michal Motyl, EricR Lai, Felix Held, Tim Chu.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61792 )

Change subject: drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
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Patch Set 6:

(2 comments)

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/61792/comment/6b5609bb_e440ff28 
PS2, Line 314: 	bool "Perform Notify Phase (Post PCI enumeration) by FSP"
> since the behavior for the amd socs stays the same by selecting to use all fsp notify calls in their kconfig files, i'm ok with the current state of this patch

Thanks Felix.

File src/soc/amd/picasso/Kconfig:

https://review.coreboot.org/c/coreboot/+/61792/comment/6f4c0c61_f3aa2158 
PS5, Line 65: 	select PROVIDES_ROM_SHARING
            : 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
            : 	select PARALLEL_MP_AP_WORK
            : 	select HAVE_SMI_HANDLER
            : 	select SSE2
            : 	select RTC
            : 	select PLATFORM_USES_FSP2_0
            : 	select FSP_COMPRESS_FSP_M_LZMA
            : 	select FSP_COMPRESS_FSP_S_LZMA
> As long as you're alphabetizing these (thanks !), might as well alphabetize lines 65-73 as well.

Ack