Patch set updated for coreboot: soc/intel/skylake: Disable Legacy PME for Root ports

[Naresh Solanki]

Naresh Solanki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17553

-gerrit

commit 59d204dced98df23d70348fdea20963b9a5f0bd6
Author: Naresh G Solanki 
Date:   Wed Nov 16 21:27:38 2016 +0530

soc/intel/skylake: Disable Legacy PME for Root ports

Legacy PME are enabled by default in FSP UPD region.
    When Legacy PME is enabled, then an SCI is generated and should be
    handled by OS and BIOS/Coreboot in collboration. OS requires some
    ACPI methods (eg _L69) which help to determine the wake source and also
    to clear some registers. But this infrastructure is not present as of
    now in coreboot and also linux handles PMEs natively.

Hence the SCI was never handled by OS and the status bits were never
    cleared i.e., PCI_EXP_STS.

For this reason the level triggered SCI will remain active and the
    system will wake up as soon as it enters S3.

To fix this, diabled Legacy PME (PmSci for Root ports).

Change-Id: I61317eb45305bdb14be3cc1a54fd9961d6ed593e
    Signed-off-by: Rizwan Qureshi 
    Signed-off-by: Naresh G Solanki 
---
 src/soc/intel/skylake/chip_fsp20.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index f90f6bc..59115a6 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
    memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,
           sizeof(params->PcieRpClkReqNumber));

+	/* disable Legacy PME */
+	memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));
+
    memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
           sizeof(params->SerialIoDevMode));