Change in coreboot[master]: soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rst

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51784 )

Change subject: soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rst
......................................................................

soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rst

Signed-off-by: Felix Held 
Suggested-by: Kangheui Won 
Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c
index cfe8779..c0b29fa 100644
--- a/src/soc/amd/common/block/acpimmio/mmio_util.c
+++ b/src/soc/amd/common/block/acpimmio/mmio_util.c
@@ -93,6 +93,11 @@
    pm_write32(PM_DECODE_EN, reg);
 }

+void fch_disable_kb_rst(void)
+{
+	pm_write8(PM_RST_CTRL1, pm_read8(PM_RST_CTRL1) & ~KBRSTEN);
+}
+
 /* PM registers are accessed a byte at a time via CD6/CD7 */
 uint8_t pm_io_read8(uint8_t reg)
 {
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 2e1da88..9360650 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -87,6 +87,7 @@
 void fch_io_enable_legacy_io(void);
 void fch_enable_ioapic_decode(void);
 void fch_configure_hpet(void);
+void fch_disable_kb_rst(void);

/* Access PM registers using IO cycles */
 uint8_t pm_io_read8(uint8_t reg);