Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 4 files changed, 26 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35678/1
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..23f010c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@
#include <stdint.h> #include <cf9_reset.h> -#include <delay.h> #include <console/console.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -246,10 +245,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..7949b69 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> -#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -209,10 +208,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d6d37d9..7ed58f6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,6 +17,8 @@ #include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> +#include <delay.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> @@ -549,14 +551,9 @@ * PCI bus 0x0a and check whether we find a device on 0:a.0 */
- /* First we reset the secondary bus */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -565,10 +562,7 @@ reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16);
- pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); + pci_s_bridge_set_secondary(p2peg, tmp_secondary);
reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -614,11 +608,9 @@ reg32 |= 1; pci_write_config32(p2peg, PEGSTS, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -774,17 +766,14 @@
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Toggle PCIRST# */ + pci_s_assert_secondary_reset(p2peg);
reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); pci_write_config32(p2peg, 0x224, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; @@ -880,6 +869,14 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); }
+void ich7_p2p_secondary_reset(void) +{ + pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); + pci_s_assert_secondary_reset(p2p_bridge); + mdelay(200); + pci_s_deassert_secondary_reset(p2p_bridge); +} + void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..fec8919 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,6 +39,8 @@ void i82801gx_enable(struct device *dev); #endif
+void ich7_p2p_secondary_reset(void); + void enable_smbus(void);
#if ENV_ROMSTAGE
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1: Code-Review+2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1: Code-Review+1
Tested on 945G-M4 board: looks good lspci: https://pastebin.com/Uj07F3EC dmesg: https://pastebin.com/3bgfBtXk
Petr Cvek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1:
(1 comment)
PCI bridge at 0:1e.0, firewire at bus 6:0.0, PCI slot is at 6:0.1, but I didn't tested it yet. No cardbus slot on kontron 986lcd-m.
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev e1) 06:00.0 FireWire (IEEE 1394): Texas Instruments TSB43AB22A IEEE-1394a-2000 Controller (PHY/Link) [iOHCI-Lynx]
https://review.coreboot.org/c/coreboot/+/35678/1/src/mainboard/kontron/986lc... File src/mainboard/kontron/986lcd-m/romstage.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/mainboard/kontron/986lc... PS1, Line 248: to cardbus add-on. 0:1e.0 is PCI slot, shared with firewire controller
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 556: pci_s_deassert_secondary_reset(p2peg); Petr, can you experiment with mdelay(25) in between with kontron/986m-lcd and add-on graphics?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 556: pci_s_deassert_secondary_reset(p2peg);
Petr, can you experiment with mdelay(25) in between with kontron/986m-lcd and add-on graphics?
Conventional PCI had Trst 1 ms minimum for RST# asserted and Trhfa 1 second when add-on hardware must be ready.
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 591: printk(BIOS_DEBUG, "PCIe link training ..."); This deserves a rewrite, lines 615-625 repeat 591-601. I think the loop below is the PCIe retry mechanism that somewhat replaced Trhfa delay in PCIe specs.
Hello Patrick Rudolph, HAOUAS Elyes, Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35678
to look at the new patch set (#2).
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/southbridge/intel/i82801gx/i82801gx.h 5 files changed, 26 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35678/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/mainboard/kontron/986lc... File src/mainboard/kontron/986lcd-m/romstage.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/mainboard/kontron/986lc... PS1, Line 248: to cardbus add-on.
0:1e. […]
Done
Petr Cvek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(3 comments)
It seems these link detection problems may be caused by the card itself. Only first run without mdelay failed (and it started to work after car replug). All runs with mdelay succeeded. Gonna do more tests tomorrow with PCIe/PCIe port multiplier. A PCIe/PCI adapter with PCI S3 trio card was detected (with and without delay).
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 556: pci_s_deassert_secondary_reset(p2peg);
Conventional PCI had Trst 1 ms minimum for RST# asserted and Trhfa 1 second when add-on hardware mus […]
OK so new infos:
I've removed HDD and RX460 GPU and added some old radeon HD4550, which I'm using for testings. I've managed to fail the detection, but after I've replugged the card it started to work. So I assume there may have been some oxidation on contacts, dry caps or something like this. Other restarts (powerdown, reset) seemed to work regardless on delay/nondelay.
A multiple powerdown/resets with delay/nondelay versions on RX460 worked always.
If a test with mdelay(10) between the old variant of assert and deassert suffices, then I can say it works. For your complete patchset I didn't have a time yet to merge it with my tree. So I guess this topic is not urgent.
ad Trhfa: yeah and according to PCI EXPRESS BASE SPECIFICATION, REV. 3.0 the value must be respected for PCIe/PCI(-X) bridge too.
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 591: printk(BIOS_DEBUG, "PCIe link training ...");
This deserves a rewrite, lines 615-625 repeat 591-601. […]
yeah the whole function should be optimized. I've some ideas for later (not relevant with reset, but with IGD init).
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200); If there is a PCI(e/-X) specification requirement for an assertion to have some duration. Maybe the easiest way is to move all mdelays into pci_s_assert_secondary_reset() function. It will shorten this patch and we can solve the problem with delay later.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
If there is a PCI(e/-X) specification requirement for an assertion to have some duration. […]
I only found 1ms Trst for RST# assertion in the specs.
I am pretty sure this 200ms was discussed once before, maybe in relation to some exotic add-on PCI hardware? It might be just a delay in general, RST# asserted or not, that was required.
commit bc8613ec
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
I only found 1ms Trst for RST# assertion in the specs. […]
I think Patrick once said, it’s related to some crypto card.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
I think Patrick once said, it’s related to some crypto card.
We built the i945 code for secunet devices, some of which come with an FPGA card (that, indeed, implements some crypto services). That card didn't like the host system booting too fast, and so we put the delay in here.
I guess it's up to Nico to decide if secunet still cares about that particular use case. If they don't support the i945 based systems anymore and/or don't see them moving to master, I'd propose removing it here. If they intend to move to master, maybe it could be put in mainboard specific code (I think that card was only used in 986lcd-m?) instead, potentially behind a flag?
But it's really up to Nico since I have no say or knowledge about the current use of these devices.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
We built the i945 code for secunet devices, some of which come with an FPGA card (that, indeed, impl […]
If we'd rebase that platform ever on master again, we'd have to validate all that again, anyway. So please just remove it.
I also doubt very much that this was ever intended. I guess somebody confused the delay *after* the reset until devices have to show up with the assertion interval? Now, I don't know PCI that well, if the reset is edge and not level triggered, it wouldn't make a difference.
In the long run, the allocator should be made aware of reset times and ensure that downstream devices get the necessary time to show up, I guess.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
Change Ifff43f095a1236c9e9a9ef0687e8efe42e72c971 already removed a similar reset delay from the Lenovo T60 romstage.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
If we'd rebase that platform ever on master again, we'd have to validate […]
It was a pretty weird situation and the delay was determined experimentally (don't think that the card's vendor would have known about the necessary delay, there was no system that booted fast enough for it to matter). That is "it works, let's ship it".
Things would be handled differently today, but that only shows how far the project has come in the ~12 years since that change was made.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
It was a pretty weird situation and the delay was determined experimentally (don't think that the ca […]
I can do a follow-up to drop ich7_p2p_secondary_reset() calls from both roda/ and kontron/, and this commit could go in its current form? Sure, this is ich7 code in i945, but not the only occasion of that.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... File src/northbridge/intel/i945/early_init.c:
https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... PS1, Line 876: mdelay(200);
I can do a follow-up to drop ich7_p2p_secondary_reset() calls from both roda/ and kontron/, and this […]
Done: CB:35765
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678 Reviewed-by: Nico Huber nico.h@gmx.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/southbridge/intel/i82801gx/i82801gx.h 5 files changed, 26 insertions(+), 35 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..c0e6071 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@
#include <stdint.h> #include <cf9_reset.h> -#include <delay.h> #include <console/console.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -246,10 +245,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to conventional PCI slot and Firewire. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..7949b69 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> -#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -209,10 +208,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d6d37d9..7ed58f6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,6 +17,8 @@ #include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> +#include <delay.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> @@ -549,14 +551,9 @@ * PCI bus 0x0a and check whether we find a device on 0:a.0 */
- /* First we reset the secondary bus */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -565,10 +562,7 @@ reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16);
- pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); + pci_s_bridge_set_secondary(p2peg, tmp_secondary);
reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -614,11 +608,9 @@ reg32 |= 1; pci_write_config32(p2peg, PEGSTS, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -774,17 +766,14 @@
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Toggle PCIRST# */ + pci_s_assert_secondary_reset(p2peg);
reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); pci_write_config32(p2peg, 0x224, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; @@ -880,6 +869,14 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); }
+void ich7_p2p_secondary_reset(void) +{ + pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); + pci_s_assert_secondary_reset(p2p_bridge); + mdelay(200); + pci_s_deassert_secondary_reset(p2p_bridge); +} + void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index d19748e..69a6413 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,8 +83,6 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */
#define PCISTS1 0x06 /* 16bit */ -#define SBUSN1 0x19 /* 8bit */ -#define SUBUSN1 0x1a /* 8bit */ #define SSTS1 0x1e /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */ #define DSTS 0xaa /* 16bit */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..fec8919 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,6 +39,8 @@ void i82801gx_enable(struct device *dev); #endif
+void ich7_p2p_secondary_reset(void); + void enable_smbus(void);
#if ENV_ROMSTAGE
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