Change in coreboot[master]: siemens/mc_apl1: Select DDR50 mode for eMMC

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/28283

Change subject: siemens/mc_apl1: Select DDR50 mode for eMMC
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siemens/mc_apl1: Select DDR50 mode for eMMC

To increase the lifetime of the circuit, it is necessary to reduce the
eMMC speed to DDR50 mode.

Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28283/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 4d9c655..a82fbfa 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -43,6 +43,9 @@
    # [6:0] steps of delay for HS200, each 125ps.
    register "emmc_rx_cmd_data_cntl2" = "0x10008"

+	# 0:HS400(Default), 1:HS200, 2:DDR50
+	register "emmc_host_max_speed" = "2"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |