Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45695 )
Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ......................................................................
mb/purism/librem_skl: Enable and set SATA tuning params
Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this.
Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier matt.devillier@puri.sm --- M src/mainboard/purism/librem_skl/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45695/1
diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index de493b0..7be8325 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -64,4 +64,10 @@ mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; }
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45695 )
Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_skl/romstage.c:
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... PS1, Line 72: mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; These are 1x SATA direct connect and 1x NVMe slot, right? In my guidelines for icfgctledatatap_fullrate (this setting), I see `1` is only valid for these two connectors and mSATA, and wanted to double-check.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45695 )
Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_skl/romstage.c:
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... PS1, Line 72: mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1;
These are 1x SATA direct connect and 1x NVMe slot, right? In my guidelines for icfgctledatatap_fullr […]
port 0 is a direct-connect SATA port, port 2 is the m.2 (SATA and NVMe)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45695 )
Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... File src/mainboard/purism/librem_skl/romstage.c:
https://review.coreboot.org/c/coreboot/+/45695/1/src/mainboard/purism/librem... PS1, Line 72: mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1;
port 0 is a direct-connect SATA port, port 2 is the m. […]
Ack
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45695 )
Change subject: mb/purism/librem_skl: Enable and set SATA tuning params ......................................................................
mb/purism/librem_skl: Enable and set SATA tuning params
Some Librems have issues with 6Gbps SATA operation on certain SSDs, setting the Receiver Equalization Boost Magnitude adjustment resolves this.
Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781 Signed-off-by: Matt DeVillier matt.devillier@puri.sm Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/purism/librem_skl/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index de493b0..7be8325 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -64,4 +64,10 @@ mem_cfg->DqPinsInterleaved = TRUE; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; }
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Patrick Georgi (Code Review)