[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)

[Nicholas Chin (Code Review)]

Attention is currently required from: Alexander Couzens, Felix Singer, Paul Menzel.

Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/74187?usp=email )

Change subject: mb/lenovo: Add ThinkCentre M900 (Skylake/LGA 1151)
......................................................................

Patch Set 3:

(18 comments)

File src/mainboard/lenovo/m900/Kconfig:

https://review.coreboot.org/c/coreboot/+/74187/comment/67dc7d46_1c69cbbd?usp... :
PS2, Line 1: if BOARD_LENOVO_M900
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/62f8cb45_d7166ca2?usp... :
PS2, Line 5: select BOARD_ROMSIZE_KB_16384
           : 	select HAVE_ACPI_RESUME
           : 	select HAVE_ACPI_TABLES
           : 	select HAVE_OPTION_TABLE
           : 	select HAVE_CMOS_DEFAULT
           : 	select INTEL_GMA_HAVE_VBT
           : 	select INTEL_INT15
           : 	select SOC_INTEL_SKYLAKE
           : 	select SKYLAKE_SOC_PCH_H
           : 	select SUPERIO_NUVOTON_COMMON_PRE_RAM
           : 	select MAINBOARD_HAS_LIBGFXINIT
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/0cc32fdf_63133bf5?usp... :
PS2, Line 27: 	hex
> Remove

Done

File src/mainboard/lenovo/m900/Kconfig.name:

https://review.coreboot.org/c/coreboot/+/74187/comment/5fc684c0_850b13ba?usp... :
PS2, Line 1: config BOARD_LENOVO_M900
>

Done

File src/mainboard/lenovo/m900/Makefile.inc:

PS2:
> Rebase and rename to Makefile. […]

Done

File src/mainboard/lenovo/m900/devicetree.cb:

PS2:
> Use chipset. […]

Done

PS2:
> A lot of the configuration here is probably wrong, as it's mostly unchanged from the H110M

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/994d82f7_dc118db3?usp... :
PS2, Line 21: 	r
> Move that under iGPU

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/5a33c8a8_abf3c4cf?usp... :
PS2, Line 53: register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
            : 			register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
            : 			register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
            : 			register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
            : 			register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
            : 			register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
            : 			register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
            : 			register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
            : 			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/d883324f_fc31e2ef?usp... :
PS2, Line 68: 			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
            : 			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
            : 			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
            : 			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
            : 			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
            : 			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
            : 			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            : 			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            : 			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
            :
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/1fa43789_f268fd59?usp... :
PS2, Line 97: register "SataPortsEnable" = "{ \
            : 				[0]     = 1, \
            : 				[1]     = 1, \
            : 				[2]     = 1, \
            : 				[3]     = 1, \
            : 			}"
> The backslashes for line continuation are not needed […]

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/49fcf8de_245cc7b7?usp... :
PS2, Line 155: 			# Set LPC Serial IRQ mode
> Seems superfluous too

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/b9198c81_bba00b02?usp... :
PS2, Line 157:
> Remove superfluous lines

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/9c1f582d_59ac6a57?usp... :
PS2, Line 159: # LPC Interface
> It's already in line 150

Done

File src/mainboard/lenovo/m900/gpio.h:

PS2:
> Look into regenerating this, as it doesn't look like the typical gpio.h format in other boards. […]

Done

File src/mainboard/lenovo/m900/hda_verb.c:

https://review.coreboot.org/c/coreboot/+/74187/comment/3a71d365_164ac3af?usp... :
PS2, Line 13: 0x411111f0
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/b42c4026_89c710d7?usp... :
PS2, Line 18: 0x411111f0
>

Done

https://review.coreboot.org/c/coreboot/+/74187/comment/c606ee40_8175777e?usp... :
PS2, Line 20: 0x411111f0
>

Done