Attention is currently required from: Nico Huber, Arthur Heymans, Kyösti Mälkki. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52922 )
Change subject: nb/amd/{agesa,pi}: Avoid overflows during DRAM calculation ......................................................................
Patch Set 2:
(3 comments)
File src/northbridge/amd/agesa/family15tn/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/1f7bb919_88db8007 PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
Yes it is gone, we would need to support at least ~256GB of DRAM memory to have any other value than […]
resource_t is uint64_t so for completeness I could add the higher DRAM limit bits.
File src/northbridge/amd/agesa/family16kb/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/37c66458_5cecfeed PS2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
As above.
Also no point in checking those since Kabini CONFIG_CPU_ADDR_BITS is 40, 40 bits are covered by 0x44 register
File src/northbridge/amd/pi/00730F01/northbridge.c:
https://review.coreboot.org/c/coreboot/+/52922/comment/713d2ab0_0a14bf08 PS2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
As above
Also for some reason, the 0x144 register is reserved on 00730F01, even in NDA BKDG. Probably removed due to max 40 physical address bits.
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Michał Żygowski (Code Review)