Attention is currently required from: Nico Huber, Arthur Heymans, Kyösti Mälkki.

View Change

3 comments:

• File src/northbridge/amd/agesa/family15tn/northbridge.c:

  • Patch Set #2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]

    Yes it is gone, we would need to support at least ~256GB of DRAM memory to have any other value than […]

    resource_t is uint64_t so for completeness I could add the higher DRAM limit bits.

• File src/northbridge/amd/agesa/family16kb/northbridge.c:

  • Patch Set #2, Line 48: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]

    As above.

    Also no point in checking those since Kabini CONFIG_CPU_ADDR_BITS is 40, 40 bits are covered by 0x44 register

• File src/northbridge/amd/pi/00730F01/northbridge.c:

  • Patch Set #2, Line 53: temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]

    As above

    Also for some reason, the 0x144 register is reserved on 00730F01, even in NDA BKDG. Probably removed due to max 40 physical address bits.

To view, visit change 52922. To unsubscribe, or for help writing mail filters, visit settings.