Change in coreboot[master]: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44891 )
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c 2 files changed, 9 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44891/1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 5a86b1c..140b775 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -180,6 +180,15 @@
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index 4be866d..d67c554 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -26,7 +26,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, }, { // WLAN @@ -40,7 +39,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, }, { // SD Reader @@ -54,7 +52,6 @@ .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, } };
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44891 )
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1:
please test before merging
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44891 )
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 1: Code-Review-1
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44891
to look at the new patch set (#2).
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/44891/2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44891 )
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44891 )
Change subject: mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree ......................................................................
mb/google/zork/dalboz: move PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork
Change-Id: I0b31466c5a991b02cef3432942f8de45805fe546 Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/44891 Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb 1 file changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index c761602..42219d7 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -180,6 +180,15 @@
register "i2c_scl_reset" = "GPIO_I2C2_SCL | GPIO_I2C3_SCL"
+ # genral purpose PCIe clock output configuration + register "gpp_clk_config[0]" = "GPP_CLK_REQ" # WLAN + register "gpp_clk_config[1]" = "GPP_CLK_REQ" # SD Reader + register "gpp_clk_config[2]" = "GPP_CLK_REQ" # NVME SSD + register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[4]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" + device cpu_cluster 0 on device lapic 0 on end end
-
Aaron Durbin (Code Review) -
Felix Held (Code Review)
-
Patrick Georgi (Code Review)