Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59011 )
Change subject: mb/google,intel: Split chromeos.c files ......................................................................
mb/google,intel: Split chromeos.c files
Move all the low-level GPIO support in bootmode.c files and build them for all stages. Keep ChromeOS related ACPI and lbtable support in chromeos.c files and build them only for ramstage.
Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/google/auron/Makefile.inc A src/mainboard/google/auron/bootmode.c M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/Makefile.inc A src/mainboard/google/beltino/bootmode.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/butterfly/Makefile.inc A src/mainboard/google/butterfly/bootmode.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootmode.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/link/Makefile.inc A src/mainboard/google/link/bootmode.c M src/mainboard/google/link/chromeos.c M src/mainboard/google/parrot/Makefile.inc A src/mainboard/google/parrot/bootmode.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/slippy/Makefile.inc A src/mainboard/google/slippy/bootmode.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/stout/Makefile.inc A src/mainboard/google/stout/bootmode.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/baskingridge/Makefile.inc A src/mainboard/intel/baskingridge/bootmode.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/Makefile.inc A src/mainboard/intel/emeraldlake2/bootmode.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/strago/Makefile.inc A src/mainboard/intel/strago/bootmode.c M src/mainboard/intel/strago/chromeos.c M src/mainboard/samsung/lumpy/Makefile.inc A src/mainboard/samsung/lumpy/bootmode.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/stumpy/Makefile.inc A src/mainboard/samsung/stumpy/bootmode.c M src/mainboard/samsung/stumpy/chromeos.c 39 files changed, 350 insertions(+), 278 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/1
diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index f642243..0ce9ace 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -2,9 +2,8 @@
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -bootblock-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_HAVE_SPD_IN_CBFS) += spd.c
diff --git a/src/mainboard/google/auron/bootmode.c b/src/mainboard/google/auron/bootmode.c new file mode 100644 index 0000000..268ff42 --- /dev/null +++ b/src/mainboard/google/auron/bootmode.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +#include "onboard.h" + +int get_write_protect_state(void) +{ + return get_gpio(CROS_WP_GPIO); +} + diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index 6872ec9..a4c8c0c 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -19,11 +19,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - return get_gpio(CROS_WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 77edc30..c1ea38b 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -2,9 +2,8 @@
bootblock-y += bootblock.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-y += chromeos.c ramstage-y += lan.c
smm-y += variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/google/beltino/bootmode.c b/src/mainboard/google/beltino/bootmode.c new file mode 100644 index 0000000..b85588e --- /dev/null +++ b/src/mainboard/google/beltino/bootmode.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} + diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 325a265..44e361c 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -20,21 +20,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 33a97f5..ecd5cc0 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -2,8 +2,8 @@
ramstage-y += ec.c
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c
diff --git a/src/mainboard/google/butterfly/bootmode.c b/src/mainboard/google/butterfly/bootmode.c new file mode 100644 index 0000000..d5a44a1 --- /dev/null +++ b/src/mainboard/google/butterfly/bootmode.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <ec/quanta/ene_kb3940q/ec.h> +#include "ec.h" +#include "onboard.h" + +int get_write_protect_state(void) +{ + return !get_gpio(WP_GPIO); +} + +int get_lid_switch(void) +{ + return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; +} + +/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ +int get_recovery_mode_switch(void) +{ + if (ENV_RAMSTAGE) + return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); + + return 0; +} + +bool mainboard_ec_running_ro(void) +{ + // TODO: MLR + // The firmware read/write status is a "virtual" switch and + // will be handled elsewhere. Until then hard-code to + // read/write instead of read-only for developer mode. + return false; +} diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 84f04be..7b37568 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -6,9 +6,7 @@
#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <ec/quanta/ene_kb3940q/ec.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" #include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) @@ -28,34 +26,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - return !get_gpio(WP_GPIO); -} - -int get_lid_switch(void) -{ - return (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1; -} - -/* FIXME: VBOOT reads this in ENV_ROMSTAGE. */ -int get_recovery_mode_switch(void) -{ - if (ENV_RAMSTAGE) - return (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO); - - return 0; -} - -bool mainboard_ec_running_ro(void) -{ - // TODO: MLR - // The firmware read/write status is a "virtual" switch and - // will be handled elsewhere. Until then hard-code to - // read/write instead of read-only for developer mode. - return false; -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index ed74d75..5f8aea2 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -1,9 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only
subdirs-y += spd -romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -verstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += lan.c
smm-y += led.c diff --git a/src/mainboard/google/jecht/bootmode.c b/src/mainboard/google/jecht/bootmode.c new file mode 100644 index 0000000..99fc54e --- /dev/null +++ b/src/mainboard/google/jecht/bootmode.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index 66a0523..de53a6b 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -6,6 +6,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <soc/chromeos.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> + #include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) @@ -20,21 +21,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 6b3f1b5..ba7e0fd 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -2,8 +2,8 @@
ramstage-y += ec.c
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
# Order of names in SPD_SOURCES is important! diff --git a/src/mainboard/google/link/bootmode.c b/src/mainboard/google/link/bootmode.c new file mode 100644 index 0000000..e543a15 --- /dev/null +++ b/src/mainboard/google/link/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c index d83fbce..82a132f 100644 --- a/src/mainboard/google/link/chromeos.c +++ b/src/mainboard/google/link/chromeos.c @@ -25,11 +25,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index f2166e1..ecd5cc0 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -2,7 +2,7 @@
ramstage-y += ec.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/google/parrot/bootmode.c b/src/mainboard/google/parrot/bootmode.c new file mode 100644 index 0000000..b7e101a --- /dev/null +++ b/src/mainboard/google/parrot/bootmode.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +int get_lid_switch(void) +{ + return get_gpio(GPIO_LID); +} + +int get_write_protect_state(void) +{ + return !get_gpio(GPIO_SPI_WP); +} + +int get_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +bool mainboard_ec_running_ro(void) +{ + return get_recovery_mode_switch(); +} diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c index 2789d38..9438b4f 100644 --- a/src/mainboard/google/parrot/chromeos.c +++ b/src/mainboard/google/parrot/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <console/console.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> @@ -32,26 +31,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_lid_switch(void) -{ - return get_gpio(GPIO_LID); -} - -int get_write_protect_state(void) -{ - return !get_gpio(GPIO_SPI_WP); -} - -int get_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -bool mainboard_ec_running_ro(void) -{ - return get_recovery_mode_switch(); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 2a2541d..f1f7023 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -2,7 +2,7 @@
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
-romstage-$(CONFIG_CHROMEOS) += chromeos.c +all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/slippy/bootmode.c b/src/mainboard/google/slippy/bootmode.c new file mode 100644 index 0000000..3a37bbd --- /dev/null +++ b/src/mainboard/google/slippy/bootmode.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 829c8b8..a198dbb 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -18,11 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc index a773a2d..a61691f 100644 --- a/src/mainboard/google/stout/Makefile.inc +++ b/src/mainboard/google/stout/Makefile.inc @@ -2,8 +2,8 @@
ramstage-y += ec.c
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c
smm-y += ec.c
diff --git a/src/mainboard/google/stout/bootmode.c b/src/mainboard/google/stout/bootmode.c new file mode 100644 index 0000000..37c0918 --- /dev/null +++ b/src/mainboard/google/stout/bootmode.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" +#include <ec/quanta/it8518/ec.h> + +int get_write_protect_state(void) +{ + return !get_gpio(GPIO_SPI_WP); +} + +int get_lid_switch(void) +{ + /* hard-code to open */ + return 1; +} + +/* + * The recovery-switch is virtual on Stout and is handled via the EC. + * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC + * indicated the recovery keys were pressed. We use a global flag for + * rec_mode to be used after RTC_POWER_STS has been cleared. + * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. + */ +int get_recovery_mode_switch(void) +{ + static int ec_in_rec_mode; + static int ec_rec_flag_good; + + if (ec_rec_flag_good) + return ec_in_rec_mode; + + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); + + u8 ec_status = ec_read(EC_STATUS_REG); + + printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", + __func__, ec_status, reg8 & RTC_BATTERY_DEAD); + + ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && + ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); + ec_rec_flag_good = 1; + return ec_in_rec_mode; +} + +bool mainboard_ec_running_ro(void) +{ + return !!get_recovery_mode_switch(); +} + diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index f2b880c..b43e9fa 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -3,15 +3,9 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/device.h> - #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> -#include "ec.h" -#include <ec/quanta/it8518/ec.h> #include "onboard.h"
void fill_lb_gpios(struct lb_gpios *gpios) @@ -34,51 +28,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - return !get_gpio(GPIO_SPI_WP); -} - -int get_lid_switch(void) -{ - /* hard-code to open */ - return 1; -} - -/* - * The recovery-switch is virtual on Stout and is handled via the EC. - * Stout recovery mode is only valid if RTC_PWR_STS is set and the EC - * indicated the recovery keys were pressed. We use a global flag for - * rec_mode to be used after RTC_POWER_STS has been cleared. - * Note, rec_mode is the only time the EC is in RO mode, otherwise, RW. - */ -int get_recovery_mode_switch(void) -{ - static int ec_in_rec_mode; - static int ec_rec_flag_good; - - if (ec_rec_flag_good) - return ec_in_rec_mode; - - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); - - u8 ec_status = ec_read(EC_STATUS_REG); - - printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", - __func__, ec_status, reg8 & RTC_BATTERY_DEAD); - - ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); - ec_rec_flag_good = 1; - return ec_in_rec_mode; -} - -bool mainboard_ec_running_ro(void) -{ - return !!get_recovery_mode_switch(); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index c69f7c8..0eec3d3 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -2,6 +2,5 @@
romstage-y += gpio.c
-romstage-y += chromeos.c -ramstage-y += chromeos.c -verstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/bootmode.c b/src/mainboard/intel/baskingridge/bootmode.c new file mode 100644 index 0000000..9e09695 --- /dev/null +++ b/src/mainboard/intel/baskingridge/bootmode.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_recovery_mode_switch(void) +{ + /* + * Recovery: GPIO69, Connected to J8E3, however the silkscreen says + * J8E2. The jump is active high. + */ + return get_gpio(GPIO_REC_MODE); +} + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index a926325..9af0f8f 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
@@ -26,21 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_recovery_mode_switch(void) -{ - /* - * Recovery: GPIO69, Connected to J8E3, however the silkscreen says - * J8E2. The jump is active high. - */ - return get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/emeraldlake2/Makefile.inc b/src/mainboard/intel/emeraldlake2/Makefile.inc index 151a3c3..a299ca6 100644 --- a/src/mainboard/intel/emeraldlake2/Makefile.inc +++ b/src/mainboard/intel/emeraldlake2/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c bootblock-y += early_init.c diff --git a/src/mainboard/intel/emeraldlake2/bootmode.c b/src/mainboard/intel/emeraldlake2/bootmode.c new file mode 100644 index 0000000..75c1db6 --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/bootmode.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +int get_recovery_mode_switch(void) +{ + /* Recovery: GPIO22, active low */ + return !get_gpio(GPIO_REC_MODE); +} + +int get_write_protect_state(void) +{ + /* Write protect is active low, so invert it here */ + return !get_gpio(GPIO_SPI_WP); +} + diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 3e17e8e..dd7a643 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
@@ -26,18 +24,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_recovery_mode_switch(void) -{ - /* Recovery: GPIO22, active low */ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - /* Write protect is active low, so invert it here */ - return !get_gpio(GPIO_SPI_WP); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 004a6a2..5a91ce9 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -2,8 +2,8 @@
bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
+all-y += bootmode.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += ec.c ramstage-y += gpio.c diff --git a/src/mainboard/intel/strago/bootmode.c b/src/mainboard/intel/strago/bootmode.c new file mode 100644 index 0000000..7775419 --- /dev/null +++ b/src/mainboard/intel/strago/bootmode.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <gpio.h> + +#include "onboard.h" + +int get_write_protect_state(void) +{ + /* + * This function might get queried early in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. + * Configuring this GPIO as input so that there isn't any ambiguity + * in the reading. + */ + if (ENV_ROMSTAGE_OR_BEFORE) + gpio_input_pullup(WP_GPIO); + + /* WP is enabled when the pin is reading high. */ + return !!gpio_get(WP_GPIO); +} + diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index e516a60..71918cf 100644 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -18,21 +18,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-int get_write_protect_state(void) -{ - /* - * This function might get queried early in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. - * Configuring this GPIO as input so that there isn't any ambiguity - * in the reading. - */ - if (ENV_ROMSTAGE_OR_BEFORE) - gpio_input_pullup(WP_GPIO); - - /* WP is enabled when the pin is reading high. */ - return !!gpio_get(WP_GPIO); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index 1fd9498..7ee0daa 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -2,8 +2,8 @@
ramstage-y += ec.c
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += gpio.c romstage-y += gpio.c diff --git a/src/mainboard/samsung/lumpy/bootmode.c b/src/mainboard/samsung/lumpy/bootmode.c new file mode 100644 index 0000000..ea777b5 --- /dev/null +++ b/src/mainboard/samsung/lumpy/bootmode.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <ec/smsc/mec1308/ec.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include "ec.h" +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} + +int get_lid_switch(void) +{ + return ec_read(0x83) & 1; +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + +bool mainboard_ec_running_ro(void) +{ + return !ec_read(0xcb); +} diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index d9db159..5fa2e63 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -3,16 +3,11 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h"
-#include "ec.h" -#include <ec/smsc/mec1308/ec.h> - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -32,38 +27,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_lid_switch(void) -{ - return ec_read(0x83) & 1; -} - -int get_power_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - return (gen_pmcon_1 >> 9) & 1; -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - -bool mainboard_ec_running_ro(void) -{ - return !ec_read(0xcb); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc index 57ec1c5..9d5e5b4 100644 --- a/src/mainboard/samsung/stumpy/Makefile.inc +++ b/src/mainboard/samsung/stumpy/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
-romstage-y += chromeos.c -ramstage-y += chromeos.c +all-y += bootmode.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c bootblock-y += gpio.c romstage-y += gpio.c
diff --git a/src/mainboard/samsung/stumpy/bootmode.c b/src/mainboard/samsung/stumpy/bootmode.c new file mode 100644 index 0000000..7aeb1d7 --- /dev/null +++ b/src/mainboard/samsung/stumpy/bootmode.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include "onboard.h" + +static bool raw_write_protect_state(void) +{ + return get_gpio(GPIO_SPI_WP); +} + +static bool raw_recovery_mode_switch(void) +{ + return !get_gpio(GPIO_REC_MODE); +} + +int get_power_switch(void) +{ + const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); + return (gen_pmcon_1 >> 9) & 1; +} + +void init_bootmode_straps(void) +{ + stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); +} diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index dd5ded2..990ec95 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -3,8 +3,6 @@ #include <bootmode.h> #include <boot/coreboot_tables.h> #include <commonlib/helpers.h> -#include <device/pci_ops.h> -#include <device/device.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -30,28 +28,6 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); }
-static bool raw_write_protect_state(void) -{ - return get_gpio(GPIO_SPI_WP); -} - -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_power_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); - u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); - return (gen_pmcon_1 >> 9) & 1; -} - -void init_bootmode_straps(void) -{ - stash_bootmode(raw_write_protect_state(), raw_recovery_mode_switch()); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
-
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