Change in coreboot[master]: soc/intel/elkhartlake: Fix PCR ID for eSPI

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61841 )

Change subject: soc/intel/elkhartlake: Fix PCR ID for eSPI
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soc/intel/elkhartlake: Fix PCR ID for eSPI

According to the Datasheet Volume 1 (doc #636112, [1]) the PCR port ID
for eSPI is 0x72 (see chapter 25.2.2). Fix it in the header file.

[1]: https://cdrdv2.intel.com/v1/dl/getContent/636112?explicitVersion=true

Test=Read and modify PCR registers of eSPI controller.

Change-Id: I5b07ef0f3a285f981791b1f4b4cdbda98ccf05ad
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61841
Reviewed-by: Arthur Heymans 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/elkhartlake/include/soc/pcr_ids.h
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h
index 20488e5..75862a6 100644
--- a/src/soc/intel/elkhartlake/include/soc/pcr_ids.h
+++ b/src/soc/intel/elkhartlake/include/soc/pcr_ids.h
@@ -25,7 +25,7 @@
 #define PID_PSF4	0xbd
 #define PID_RTC		0xc3
 #define PID_ITSS	0xc4
-#define PID_ESPI	0xc7
+#define PID_ESPI	0x72
 #define PID_SERIALIO	0xcb

#endif